74LVTH245 Datasheet

  • 74LVTH245

  • Low Voltage Octal Bidirectional Transceiver

  • 85.68KB

  • Fairchild

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74LVT245 鈥?74LVTH245 Low Voltage Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs
November 1999
Revised March 2005
74LVT245 鈥?74LVTH245
Low Voltage Octal Bidirectional Transceiver
with 3-STATE Inputs/Outputs
General Description
The LVT245 and LVTH245 contain eight non-inverting bidi-
rectional buffers with 3-STATE outputs and are intended for
bus-oriented applications. The Transmit/Receive (T/R)
input determines the direction of data flow through the bidi-
rectional transceiver. Transmit (active-HIGH) enables data
from A ports to B ports; Receive (active-LOW) enables
data from B ports to A ports. The Output Enable input,
when HIGH, disables both A and B ports by placing them in
a HIGH Z condition.
The LVTH245 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
These transceivers are designed for low-voltage (3.3V)
V
CC
applications, but with the capability to provide a TTL
interface to a 5V environment. The LVT245 and LVTH245
are fabricated with an advanced BiCMOS technology to
achieve high speed operation similar to 5V ABT while
maintaining a low power dissipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH245),
also available without bushold feature (74LVT245)
s
Live insertion/extraction permitted
s
Power Up/Down high impedance provides glitch-free
bus loading
s
Outputs source/sink,

32 mA/

64 mA
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human-body model
!
2000V
Machine model
!
200V
Charged-device model
!
1000V
Ordering Code:
Order Number
74LVT245WM
74LVT245SJ
74LVT245MSA
74LVT245MTC
74LVT245MTCX_NL
(Note 1)
74LVTH245WM
74LVTH245SJ
74LVTH245MSA
74LVTH245MTC
74LVTH245MTCX_NL
(Note 1)
Package
Number
M20B
M20D
MSA20
MTC20
MTC20
M20B
M20D
MSA20
MTC20
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
鈥淿NL鈥?indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
漏 2005 Fairchild Semiconductor Corporation
DS500203
www.fairchildsemi.com

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