CY7C4425-25JC Datasheet

IC型号：
CY7C4425-25JC
PDF描述：
64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs
文件大小：
216.22KB
PDF页数：
0页
芯片厂家：
CYPRESS

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1CY 7C42 25

fax id: 5410

CY7C4425/4205/4215

CY7C4225/4235/4245

64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs

Features

鈥?High-speed, low-power, first-in first-out (FIFO)

memories

鈥?64 x 18 (CY7C4425)

鈥?256 x 18 (CY7C4205)

鈥?512 x 18 (CY7C4215)

鈥?1K x 18 (CY7C4225)

鈥?2K x 18 (CY7C4235)

鈥?4K x 18 (CY7C4245)

鈥?High-speed 100-MHz operation (10 ns read/write cycle

time)

鈥?Low power (I

=45 mA)

鈥?Fully asynchronous and simultaneous read and write

operation

鈥?Empty, Full, Half Full, and Programmable Almost

Empty/Almost Full status flags

鈥?TTL-compatible

鈥?Retransmit function

鈥?Output Enable (OE) pin

鈥?Independent read and write enable pins

鈥?Center power and ground for reduced noise

鈥?Supports free-running 50% duty cycle clock inputs

鈥?Width Expansion Capability

鈥?Depth Expansion Capability

鈥?Space saving 64-pin 10x10 TQFP, and 14x14 TQFP

鈥?68-pin PLCC

controlled by a free-running clock (WCLK) and a write enable

pin (WEN).

When WEN is asserted, data is written into the FIFO on the

rising edge of the WCLK signal. While WEN is held active, data

is continually written into the FIFO on each cycle. The output

port is controlled in a similar manner by a free-running read

clock (RCLK) and a read enable pin (REN). In addition, the

CY7C42X5 have an output enable pin (OE). The read and

write clocks may be tied together for single-clock operation or

the two clocks may be run independently for asynchronous

read/write applications. Clock frequencies up to 100 MHz are

achievable.

Retransmit and Synchronous Almost Full/Almost Empty flag

features are available on these devices.

Depth expansion is possible using the cascade input (WXI,

RXI), cascade output (WXO, RXO), and First Load (FL) pins.

The WXO and RXO pins are connected to the WXI and RXI

pins of the next device, and the WXO and RXO pins of the last

device should be connected to the WXI and RXI pins of the

first device. The FL pin of the first device is tied to V

and the

FL pin of all the remaining devices should be tied to V

The CY7C42X5 provides five status pins. These pins are de-

coded to determine one of five states: Empty, Almost Empty,

Half Full, Almost Full, and Full (see

Table 2).

The Half Full flag

shares the WXO pin. This flag is valid in the standalone and

width-expansion configurations. In the depth expansion, this

pin provides the expansion out (WXO) information that is used

to signal the next FIFO when it will be activated.

The Empty and Full flags are synchronous, i.e., they change

state relative to either the read clock (RCLK) or the write clock

(WCLK). When entering or exiting the Empty states, the flag is

updated exclusively by the RCLK. The flag denoting Full states

is updated exclusively by WCLK. The synchronous flag archi-

tecture guarantees that the flags will remain valid from one

clock cycle to the next. As mentioned previously, the Almost

Empty/Almost Full flags become synchronous if the

/SMODE is tied to V

. All configurations are fabricated

using an advanced 0.65碌 N-Well CMOS technology. Input

ESD protection is greater than 2001V, and latch-up is prevent-

ed by the use of guard rings.

Functional Description

he CY7C42X5 are high-speed, low-power, first-in first-out

(FIFO) memories with clocked read and write interfaces. All

are 18 bits wide and are pin/functionally compatible to

IDT722x5. The CY7C42X5 can be cascaded to increase FIFO

depth. Programmable features include Almost Full/Almost

Empty flags. These FIFOs provide solutions for a wide variety

of data buffering needs, including high-speed data acquisition,

multiprocessor interfaces, and communications buffering.

These FIFOs have 18-bit input and output ports that are con-

trolled by separate clock and enable signals. The input port is

Cypress Semiconductor Corporation

鈥?/div>

3901 North First Street

鈥?/div>

San Jose

鈥?/div>

CA 95134 鈥?/div>

408-943-2600

April 1995 - Revised August 18, 1997

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