DM74LS393 Dual 4-Bit Binary Counter
August 1986
Revised March 2000
DM74LS393
Dual 4-Bit Binary Counter
General Description
Each of these monolithic circuits contains eight master-
slave flip-flops and additional gating to implement two indi-
vidual four-bit counters in a single package. The
DM74LS393 comprises two independent four-bit binary
counters each having a clear and a clock input. N-bit binary
counters can be implemented with each package providing
the capability of divide-by-256. The DM74LS393 has paral-
lel outputs from each counter stage so that any submultiple
of the input count frequency is available for system-timing
signals.
Features
s
Dual version of the popular DM74LS93
s
DM74LS393 dual 4-bit binary counter with individual
clocks
s
Direct clear for each 4-bit counter
s
Dual 4-bit versions can significantly improve system
densities by reducing counter package count by 50%
s
Typical maximum count frequency 35 MHz
s
Buffered outputs reduce possibility of collector commu-
tation
Ordering Code:
Order Number
DM74LS393M
DM74LS373N
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Function Table
Counter Sequence
(Each Counter)
Count
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
H
=
HIGH Logic Level
L
=
LOW Logic Level
Outputs
Q
D
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
Q
C
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
Q
B
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
Q
A
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
漏 2000 Fairchild Semiconductor Corporation
DS006434
www.fairchildsemi.com
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