DS1218
Nonvolatile Controller
www.dalsemi.com
FEATURES
Converts CMOS RAM into nonvolatile
memories
Unconditionally write protects when V
CC
is
out of tolerance
Automatically switches to battery when
power fail occurs
Space saving 8-pin mini-DIP/8-pin 150 mil
SOIC
Consumes less than 100 na of battery current
PIN ASSIGNMENT
V
CCO
NC
NC
GND
1
2
3
4
8
7
6
5
V
CCI
V
BAT
CEO
CEI
PIN DESCRIPTION
V
CCI
V
CCO
CEI
NC
CEO
V
BAT
GND
- Input +5 Volt Supply
- RAM Power (V
CC
) Supply
- Chip Enable Input
- No Connection
- Chip Enable Output
- + Battery
- Ground
DESCRIPTION
The DS1218 is a CMOS circuit which solves the application problems of converting CMOS RAM into
nonvolatile memory. Incoming power is monitored for an out-of-tolerance condition. When such a
condition is detected, the chip enable output is inhibited to accomplish write protection and the battery is
switched on to supply RAM with uninterrupted power. Special circuitry uses a low-leakage CMOS
process which affords precise voltage detection at extremely low battery consumption. The 8-pin mini-
DIP package keeps PC board real estate requirements to a minimum. By combining the DS1218
nonvolatile controller chip with a full CMOS memory and lithium batteries, 10 years of nonvolatile RAM
operation can be achieved.
OPERATION
The DS1218 Nonvolatile Controller performs the circuit functions required to battery back-up a RAM.
First, a switch is provided to direct power from the battery or V
CCI
supply, depending on which is greater.
This switch has a voltage drop of less than 0.2V. The second function which the nonvolatile controller
provides is power-fail detection. The DS1218 constantly monitors the V
CC
supply. When V
CCI
falls to
1.26 times the battery voltage, a precision comparator outputs a power-fail detect signal to the chip enable
logic. The third function of write protection is accomplished by holding the chip enable output signal to
within 0.2V of the V
CCI
or battery supply, when a power-fail condition is detected.
During nominal supply conditions, the chip enable output will follow chip enable input with a maximum
propagation delay of 10 ns.
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