鈥?/div>
AND-Gated ( Enable/Disable) Serial Inputs
Fully Buffered Clock and Serial Inputs
Direct Clear
Package Options Include Plastic
Small-Outline (D) Packages and Standard
Plastic (N) 300-mil DIPs
D OR N PACKAGE
(TOP VIEW)
description
7
8
This 8-bit parallel-out serial shift register features
AND-gated serial (A and B) inputs and an
asynchronous clear (CLR) input. The gated serial
inputs permit control over incoming data because a low at either input inhibits entry of the new data and resets
the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which
determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low,
provided that the minimum setup-time requirements are met. Clocking occurs on the low-to-high-level transition
of the clock (CLK) input. All inputs are diode clamped to minimize transmission-line effects.
A
B
Q
A
Q
B
Q
C
Q
D
GND
1
2
3
4
5
6
14
13
12
11
10
9
V
CC
Q
H
Q
G
Q
F
Q
E
CLR
CLK
The SN74ALS164A is characterized for operation from 0掳C to 70掳C.
FUNCTION TABLE
INPUTS
CLR
L
H
H
H
H
CLK
X
L
鈫?/div>
鈫?/div>
鈫?/div>
A
X
X
H
L
X
B
X
X
H
X
L
QA
L
QA0
H
L
L
OUTPUTS鈥?/div>
Q B . . . QH
L
QB0
QAn
QAn
QAn
L
QH0
QGn
QGn
QGn
鈥?QA0, QB0, QH0 = the level of QA, QB, or QH, respectively,
before the indicated steady-state input conditions were
established.
H = high level (steady state), L = low level (steady state)
X = irrelevant (any input, including transitions)
鈫?/div>
= transition from low to high level
QAn, QGn = the level of QA or QG before the most recent
鈫?/div>
transition of the clock; indicates a 1-bit shift.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1994, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1
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