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全面理解非易失存储器(Flash,EPROM,EEPROM) PDF版已提供下载 |
| 作者：code631 栏目：集成电路 |
看到很多朋友问及非易失存储器的问题，手头有一份很好的材料，于是就有翻译成中文给大家讨论的念头，希望能给大家一些帮助。 PDF Version download here: http://file.21ic.com.cn/songfei/17－综合类资料/全面理解非易失存储器.pdf 版权申明： 该文章为翻译作品 原作者：Jitu J.Makwana, Dr.Dieter K.Schroder 翻译者：GongYi（INFINEON TECHNOLOGIES, MEMORY development center） email: code631@gmail.com 转贴请注明以上信息，谢谢合作。 * - 本贴最后修改时间：2006-3-30 15:48:06 修改者：code631 |
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| 作者： code631 于 2005/12/21 0:28:00 发布：
非易失存储器概论 非易失存储器概论 作者：Jitu J.Makwana, Dr.Dieter K.Schroder 翻译：GongYi(INFINEON TECHNOLOGIES,MEMORY development center） Email: code631@gmail.com 前言 本文论述了基本非易失存储器（NVM）的基本概念。第一部分介绍了NVM的基本情况，包括NVM的背景以及常用的存储器术语。第二部分我将介绍怎样通过热电子注入实现NVM的编程。第三部分包括了用FOWLER-NORDHEIM 隧道效应实现对NVM的擦除。同时，简单的FN隧道效应的原理也将在这里给大家做一个说明。第四部分介绍了用于预测NVM编程特性的模型—热电子注入机制所依赖的“幸运电子”模型。最后一部分介绍了NVM可靠性方面的问题，如数据保持能力（DATA RETENTION）,耐久力（ENDURANCE）,和干扰（DISTURB）。 关键字：非易失，存储器，热电子注入，隧道效应，可靠性，数据保持，耐久力，干扰，闪存 * - 本贴最后修改时间：2006-4-1 7:13:14 修改者：code631 |
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| 作者： code631 于 2005/12/21 0:29:00 发布：
第一部分： 介绍 第一部分： 介绍 存储器大致可分为两大类：易失和非易失。易失存储器在系统关闭时立即失去存储在内的信息；它需要持续的电源供应以维持数据。大部分的随机存储器（RAM）都属于此类。非易失存储器在系统关闭或无电源供应时仍能保持数据信息。一个非易失存储器（NVM）器件通常也是一个MOS管，拥有一个源极，一个漏极，一个门极另外还有一个浮栅（FLOATING GATE）。它的构造和一般的MOS管略有不同：多了一个浮栅。浮栅被绝缘体隔绝于其他部分。 非易失存储器又可分为两类：浮栅型和电荷阱型。Kahng 和 Sze 在1967年发明了第一个浮栅型器件，在这个器件中，电子通过3nm厚度的氧化硅层隧道效应从浮栅中被转移到substrate中。隧道效应同时被用于对期间的编程和擦除，通常它适用于氧化层厚度小于12nm。 储存在浮栅中的电荷数量可以影响器件的阈值电压（Vth）,由此区分期间状态的逻辑值1或0。 在浮栅型存储器中，电荷被储存在浮栅中，它们在无电源供应的情况下仍然可以保持。所有的浮栅型存储器都有着类似的原始单元架构。他们都有层叠的门极结构如图一所示。第一个门极被埋在门极氧化层和极间氧化层之间，极间氧化层的作用是隔绝浮栅区，它的组成可以是氧-氮-氧，或者二氧化硅。包围在器件周围的二氧化硅层可以保护器件免受外力影响。第二个门极被称为控制门极，它和外部的电极相连接。浮栅型器件通常用于EPROM(Electrically Programmable Read ONLY MEMORY)和EEPROM(Electrically Erasable and Programmable Read ONLY MEMORY)。
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| 作者： code631 于 2005/12/21 0:31:00 发布：
1 电荷阱型器件是在1967年被发明的，也是第一个被发明的电编程半导体器件。在这类型的存储器中，电荷被储存在分离的氮阱中，由此在无电源供应时保持信息。电荷阱器件的典型应用是在MNOS(METAL Nitride Oxide SILICON)，SNOS(SILICON Nitride Oxide SEMICONDUCTOR)和SONOS(SILICON Oxide Nitride Oxide SEMICONDUCTOR)中。图二展示了一个典型的MNOS电荷阱型存储器的结构。  MNOS中的电荷通过量子机制穿过一层极薄的氧化层（一般为1.5-3nm）从沟道中被注入氮层中。 世界上第一个EPROM,是一个浮栅型器件，是通过使用高度参杂的多晶硅（poly-Si）作为浮栅材料而制成的，它被称为浮栅雪崩注入型MOS存储器（FAMOS）。它的门极氧化层厚度为100nm, 由此保护电荷流向substrate。 对存储器的编程是通过对漏极偏压到雪崩极限使得电子在雪崩中从漏极区域被注入到浮栅中。这种存储器的擦除只能通过紫外线照射或X光照射。如今，这种EPROM的封装形式通常是陶瓷带有一个可透光的小窗口，或者是一个塑料封装的没有石英窗的。这些存储器被称为一次性编程存储器（OTP）,这种存储器很便宜，但是在封装后要测试他们是不可能的。带有石英窗口的EPROM价格比较贵，但是由于可被擦除，所以可以在封装后作另外的测试。 虽然在70年代有了紫外可擦除型的商业用非易失存储器，研制电可擦写型非易失存储器的吸引力正在逐渐扩大。 H.IIZUKA et.al 发明了第一个电可擦写型非易失存储器，被称为叠门雪崩注入型MOS(SAMOS)存储器。SAMOS存储器由两个多晶硅门和一个外部控制门组成。外部控制门的出现使得电可擦写成为了现实，并且提高了擦除的效率。电可擦写型非易失存储器的电擦除是通过将浮栅中的电荷量恢复到未注入时的水平实现的。比起紫外照射擦除产品，这种产品的封装成本低廉很多。缺点是单位存储单元的尺寸要比以前大很多，使得晶元面积也大了很多。EEPROM单元由两个晶体管组成，一个是浮栅晶体管，另一个是选择晶体管，如图三所示。选择晶体管是用于在编程和擦除时选择相应的浮栅晶体管。后来，由于加入了错位修正电路以及修补电路，晶元尺寸被再次增大。  在80年代，一个经典的非易失存储器产品被发明了，那就是闪存。第一个闪存产品通过热电子注入机制实现对器件编程，而擦除则采用了隧道效应。这种新型的存储器只能被整片或一个区域的删除而不能被单字节删除。因此，选择晶体管被移除了，由此也减小了单元的尺寸。典型的单元结构如图一所示。 * - 本贴最后修改时间：2005-12-21 0:36:02 修改者：code631 |
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| 作者： code631 于 2005/12/21 18:06:00 发布：
2 第二部分 基本编程机制 无论是浮栅型或电荷阱型存储器，对器件编程都是通过将电子注入浮栅区或者氮层区中。实现此过程，主要是通过两种的机制：FN 隧道效应（对薄氧化层）以及热电子注入。 1． Fowler-Nordheim 隧道效应 FN隧道效应是NVM最主要的电荷注入方式之一，在对器件编程时，在控制门极加上很大的电压（Vcg），能带结构会如图四变化：  在图四中，ec 和 ev 分别是导带和禁带，Eg 为能带宽度 (硅材料是1.1 eV ), fb 为Si-SiO2 能量势垒 (fb is 3.2 eV for electrons and 4.7 eV for holes). 外加电压 Vcg 造成电势提供给substrate中的电子通过薄氧化层中的隧道到达浮栅区的可能。弯曲的IPD和门氧化层能带是不同的，这是由于它们的厚度不同。IPD厚度从25nm到45nm不等，而门氧化层厚度只有5nm到12nm。电子到达浮栅区而形成的电流密度为：    其中, h = 普朗克常数 = 诸如表面能量势垒 (3.2 eV for Si-SiO2) q = 单个电子电量 (1.6x10-19 C) m = 自由电子质量 (9.1x10-31 kg) m* = 二氧化硅能带中自由电子有效质量 (0.42 m) Vinj = 注入表面电势 Vapp = 门氧化层两侧电势 (V) Vfb = 平带电势(V) tox = 门氧化层厚度 (cm) 等式 1 隧道电流密度和加在门氧化层两侧电势Vapp成指数比， 从而影响诸如表面电势Vinj。图五展示了一个NVM的横截面，其电子隧道效应电流成均匀分布。Vcg 正电压，源极Vs 和漏极 Vd, 以及substrate Vsub 都接地。  另一个可选的对FLASH编程的方法如图六所示，被称为漏极隧道效应。此方法有时比均匀隧道效应编程在编程速度方面更有利，由于注入面积很小，产生的隧道电流密度更大。  * - 本贴最后修改时间：2005-12-21 18:07:49 修改者：code631 |
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| 6楼： | >>参与讨论 |
| 作者： code631 于 2005/12/22 20:46:00 发布：
基本编程机制：热电子注入 2，热电子注入 NVM 也可以通过热电子注入来实现编程。对于在p型substrate上的n型NVM使用热电子注入，而在n型substrate上的p型NVM则采用热空穴注入。热空穴注入的速度非常慢，这是因为空穴质量和Si-SiO2 能带势垒（4.7 eV ）, 这也是现在绝大多数NVM生产商都采用p型substrate上n型NVM的原因。 通常存储器单元是在漏极侧夹断区向浮栅区进行热电子注入。这些热电子通过在漏极偏置电压得到能量，并且被水平偏置电压加速Elat，到达漏极附近拥有更高的电势的耗尽区域。当这些电子得到足够能量足以超过substrate和门氧化层之间的能量势垒3.2 eV时，由于加在门氧化层两侧的Vd ，它们能够被注入门氧化层中，当一个高的正向电势 Vcg 被加载于控制门极时，这些电子被吸引到了浮栅区中。此时能带变化如图七。  图七，浮栅型存储器单元在热电子注入时能带图 当浮栅被足够数量电子注入后，注入电流Ig 被减弱到几乎为0。这是因为氧化层电势Eox (在开始时用于吸引电子) 现在则排斥电子。Vcg 增加了浮栅中的电荷量同时 Vd 则影响了编程速度. 图八展示了一个利用热电子注入实现编程的NVM的横截面。 Vcg 和 Vd 为正向电压分别为15 V 和 10 V 而 Vs 和 Vsub 则接地。  |
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| 作者： code631 于 2005/12/22 20:50:00 发布：
第三部分： 基本擦除机制 第三部分： 基本擦除机制 第二部分论述了两种编程机制，FN 隧道效应以及热电子注入。为了能够再次对NVM编程，之前需要对NVM擦除。本章将论述在工业界最常应用的NVM擦除机制。 被注入浮栅之中的电子被门/氧化层能量势垒（3.2 eV）保持在其中。而在氧化层/硅接触面的电压能量势垒也大于3.0 eV，因此， 电子自然迁移的可能性很小。浮栅内储存的电子使得器件的阈值电压增大。 通常存在两种擦除方法： 1. 紫外线照射 2. FN 隧道效应 IIIa. 紫外线照射 根据图九所示，电子由紫外线照射获得足够的能量，足以克服能量势垒由浮栅区到达控制门区或者substrate区，导致期间的阈值电压降低。一般来说，阈值电压从高电位降低到中电位所需要的时间大约为10分钟。  图九，紫外擦除NVM的能带图 IIIb. FN 隧道效应 FU 隧道效应也用于对NVM的擦除，方法之一是对控制门极加高负电压。这时能带变化如图十所示。所加的电压Vcg 形成的电场造成了一个电势势垒，它给浮栅中的电子提供了一条由浮栅到达substrate的通路。  图十，浮栅NVM进行FN擦除时的能带图 图十一a和b展示了两种不同的FN擦除方法：均匀隧道效应和漏极区域隧道效应。第一种方法中，只需要一个很大的负电压被加载在控制门极；而第二种方法中，除了此负电压之外，还需要在漏极加载一个正电压。   总的来说，均匀隧道效应擦除要比漏极区域隧道效应擦除慢，但是后者可能会造成器件可靠性问题：由于集中电子隧穿造成的漏极区门氧化层破坏。 |
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| 作者： code631 于 2005/12/22 20:54:00 发布：
第四部分： 热载流子注入模型 第四部分： 热载流子注入模型 热电子注入是对FLASH EEPROM编程的一种手段，它利用高电场加速得到的热电子注入浮栅区来实现电子的移动。此方法编程速度比较慢，这是因为电子注入效率很低，其依据是建立在可能性的统计学规律之上。热电子注入机制也增加了漏极区域的电离，多子和少子都被电离产生。高动能的空穴通常被substate所收集从而形成substrate电流 (Isub)而电子则被漏极区域收集形成漏极电流 (Ids)。此时，如果氧化层电场(Eox)吸引电子，那么这些载流子将克服能量势垒通过氧化层到达浮栅区形成门极注入电流(Ig)。有两个模型用于描述热电子注入： 1， 幸运电子模型 2， 有效电子温度模型 IVa.幸运电子模型和高阈值电压 VT 幸运电子模型是由肖特基建立的，理论上来说它可以这么来解释：为了使热电子能够到达浮栅区，热电子必须在垂直沟道电势差中得到足够的动能 (Elat) 使得它具有足够的动力克服二氧化硅能量势垒到达Si-SiO2 接触。图十二展示了幸运电子模型的概念。它必须具备三个条件： A - B：一个沟道电子由Elat 得到能量而变成热电子。它的动能必须被重新引导至Si-SiO2 接触面。假设此过程的可能性为 -- 一个电子获得足以克服Si-SiO2能量势垒的能量的可能性。 B – C：此热电子必须不能被碰撞而丧失能量。这一过程的可能性为PSEMI 。PSEMI 被定义为一个电子在Si-SiO2 接触面穿过而不被碰撞的可能性。 C – D： 电子在Si-SiO2 接触面移动到浮栅区过程中，它必须不被氧化层中的电势阱所吸引。此过程的可能性为Pinsul – 电子不被氧化层中电势阱所吸引的可能性。  图十二，幸运电子模型能带图 由于以上三个可能性在统计学上互相独立，总可能性即为三者之乘积。那么门极电流可以得出：  其中： lr = 动能散射平均路径长度 = 92 nm Leff = 有效沟道长度 (cm) Ids = 漏极- 源极电流(A) 浮栅区的电荷量改变了器件的阈值电压：  其中： DVT = VT (Programmed) - VT (Initial) DQfg = Qfg (Programmed) - Qfg (Initial) = 浮栅区电荷量变化 电荷量变化也等于  其中：Dt为编程时间（s） 器件阈值电压由初始值到现在的变化为：  其中： Cfg = 浮栅到控制门极的电容量(F) 图十三展示了一个典型的传输特性曲线，可以看出Ids-Vcg 曲线是相互平行的。他们的位移相当于DQfg/ Cfg。  |
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| 9楼： | >>参与讨论 |
| 作者： code631 于 2005/12/22 20:59:00 发布：
第五部分： NVM可靠性问题 第五部分： NVM可靠性问题 NVM存储器单元有几个重要的功能性参数，用于评估单元的性能。这些参数基本可以分为两大类：耐久力和数据保持能力。为了更好的理解这些概念，我们有必要了解一些关于门氧化层，IPD的完整性知识。无论在EPROM， EEPROM还是FLASH EEPROM中，影响器件可靠性的关键在于门氧化层和IPD的质量。 门氧化层主要的失效机制涉及到在热电子或者FN注入时由高电场引起的氧化层击穿和阱陷。有研究发现氧化层缺陷和硅氧踺断裂造成阱陷。氧化层击穿通常发生于通过单位面积的电荷数量(Qbd)超过一定水平之后，通常也和外加电场强度有关。Qbd是个工业标准电气性能测试，用于测量氧化层在高浓度Qbd情况下的表现。阱陷的定义是在对单元编程时造成的电子在氧化层中被困住的现象。这种现象改变了注入区域物理特性，因此，被转移到浮栅区的电子数量以及其间阈值电压也被改变。 此前已经提到过IPD,它通常用于隔绝浮栅区和其他区域，所以理论上它必须是无缺陷以防止漏电流的产生。由于浮栅是由多晶硅构成的，通常是在IPD生长工艺过程中被氧化的。氧化的过程导致在grain 边缘增强从而改变了多晶硅表面的物理结构，形成了小隆起状表面。这些表面的不平整导致了局部电场的变化，引发了高漏电流。影响IPD质量的其中一个因素是多晶硅层的参杂和多晶硅沉淀，氧化时的温度控制。多种绝缘材料并用，可以减少缺陷密度和提高电场均匀度如氧-氮-氧现在被广泛应用于IPD中以防止漏电流的产生。在此材料中，浮栅电子被氮氧层困住，从而形成与漏电流反向的电场，进一步减小漏电流的扩大。通常ONO层厚度为5 - 10 nm（底层氧化）, 20 nm（氮层）, 3 nm（顶层氧化）。底层氧化是在浮栅区上面，而顶层氧化位于控制门极下面。  图十四，由于表面不平整引发的IPD 漏电流 Va. 耐久力特性 耐久力特性表现于存储器的阈值电压区间，它与编程次数有密切的关系，如图十五所示。NVM可以被编程和擦除直到氧化层被破坏。这也意味着NVM有效的可编程次数是有限的，举例来说大部分商用EEPROM产品可以保证106 有效编程次数。此情况下氧化层的破坏通常被称为氧化层的降级，而一个存储器可以经受的最大编程次数被称为耐久力。阈值电压窗口关闭通常发生在两者值（高电平与低电平状态）太小以至不能被明显区分。这种现象归咎于电子被氧化层中原有的电子阱陷所困住无法再移动，另有实验证明阱陷是在对单元编程或者擦除过程中氧化层两端加载的高电场所产生的。因此，门氧化层的质量对于器件耐久力尤其重要。  图十五，典型的EEPROM单元阈值电压窗口关闭 Vb. 数据保持能力特性 当一个NVM单元无法保持浮栅中的电荷量时，我们称之为数据保持能力的丧失。数据保持能力是衡量一个NVM存储器单元在无电源供应情况下可以保持数据的时间。在浮栅型存储器中，存储在浮栅区的电荷会通过门氧化层和IPD流失。由自由电子（离子）移动和氧化层中缺陷所产生的漏电流，会导致单元阈值电压的改变。不同的电子流失方式有：温度引起的电离，电子中和，由于正离子污染引发的流失。为了提高单元的保持数据能力，人们采用了不同的手段来提高门氧化层和IPD的质量。 数据保持能力可以用估计生命周期来量化，当电荷流失发生时，单元的阈值电压变化如下：  其中dQFG, CFG, 和 dVT 分别为浮栅区电荷变化，浮栅电容量和单元阈值电压。等式9展示了流失电子的数量，等式10则展示了流失电子数量和形成的漏电流的关系以及保持时间。   对于典型的 CFG = 30 fF 和 VT 变化为3 V，从浮栅区到控制门区电子流失的数量 大约为 5.6x105个。表格 1 展示了保持时间 dt，对于不同的 ILeakage 相关与5.6x105 电子流失或相当于3 V VT变化。 Leakage Current, ILeakage (A) Retention Time, dt (Years) 1x10-20 0.28 5x10-21 0.56 1x10-21 2.84 5x10-22 5.68 2.85x10-22 10 表格一，数据保持时间与ILeakage 由表一可以看出普通的NVM阈值电压降低3V，漏电流为2.85x10-22 A的情况下总共需要10年。 Vc存储器干扰 大规模的在生产中使用NVM需要他们具有10年以上的数据保持能力。一个存储器单元阵列在编程和擦除中经受STRESS被称为干扰。具体而言有四种：dc erase, dc program, program disturb,和read disturb。在编程过程中最常见的两种干扰是dc program和program disturb，在擦除过程中最常见的则是dc erase，最后在读过程中的干扰被称为read disturb。图十六展示了一个存储器单元阵列电路图，它将被用于解释干扰现象。  图十六，用于解释干扰现象的电路图 在上图中，存储器单元阵列的列连接着每个单元的漏极，(COL 1, COL 2, and COL 3) 被称为位线，而阵列的行连接着每个单元的控制门极 (ROW 0 and ROW 1) 被称为字线。在前面关于热电子注入的讨论中已经说过，在对存储器编程时需要同时在位线和字线加载电压。 下面来讨论这四种不同的干扰： 1) DC Erase: 这种类型的干扰通常发生在已经被编程的单元(Cell A)。那些在与被编程的单元在同一条字线 (ROW 1) 的单元正在被编程(COL 2 and ROW 1)。在此期间ROW 1 被加载一个高电压15 V，由此产生的一个高电场出现在IPD的两侧。这个电压可能导致电子从浮栅区移动到控制门区，结果是电荷流失造成单元的阈值电压减小。 2) DC Program: 也被称为gate disturb，发生于当未被编程的或者已擦除的单元 (Cell B)。这些未编程的单元与正在被编程的单元在同一字线上 (ROW 1) 。这些单元只有很少量的电子在浮栅中，因此他们的阈值电压是低电平的。当ROW1加载15V时，通过门极氧化层的电场变得被得很强，这一电场可能导致电子进入浮栅区从而提高阈值电压。这种情况下，我们称之为软编程。 3) Program Disturb: 通常也成为drain-disturb，只发生于被编程过的单元。一个被编程过的单元 (Cell C) 与正在被编程的单元 (COL 2 和 ROW 1)共享一条位线。在它的浮栅/漏极区有一个高电场存在。这一高电场导致了电子从浮栅区移向漏极区从而导致阈值电压减小。 4) Read Disturb: 这种干扰机制发生于与正在被读的单元共享一条字线的擦除过的单元。共享的字线上的擦除电压为5V，被选中的单元漏极偏置为1V，未选择单元的源极，漏极，和substrate均为0V。 |
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| 10楼： | >>参与讨论 |
| 作者： code631 于 2005/12/22 21:00:00 发布：
VI. 结论 VI. 结论 本文主要介绍了NVM的发展过程和技术概况。主要的编程手段有热载流子注入和FN隧道效应。在FN隧道效应中，门极氧化层厚度一般小于12nm，而在热电子注入中可以厚很多。两种典型的擦除机制为紫外照射和FN隧道效应，通常在UV EPROM中使用紫外照射擦除的方法，而在EEPROM和FLASH存储器中则使用了FN隧道效应擦除机制。紫外擦除所需的时间一般为10分钟而FN隧道效应擦除的时间根据控制门极和漏极上加载的电压强度不同仅为1ms到10ms。最快的编程机制是热电子注入，一般只需100MS。在此过程中，我们讨论了幸运电子模型，这个模型揭示了门电流是如何通过可能性模型来计算的过程。虽然注入的效率很低，但将热电子注入浮栅的过程是很快的，这是因为有外加强电场的作用。对于每个NVM器件来说，可靠性的问题都存在，而耐久力和数据保持力是最重要的两个问题。此外，在编程中和擦除中产生的干扰也是影响NVM可靠性的一个因素。 References [1] Kahng, D. and Sze, S. M. (1967) A floating gate and its application to MEMORY DEVICEs. Bell Systems Technical Journal. 46, 1283. [2] Wegener, H. A. R, Lincoln, A. J., Pao, H. C., O'Connell, M. R., and Oleksiak, R. E. (1967) The variable threshold TRANSISTOR, a new electrically alterable, non-destructive read-only storage DEVICE. IEEE IEDM Technical Digest. 1. [3] Wegener, H. A. R, Lincoln, A. J., Pao, H. C., O'Connell, M. R., and Oleksiak, R. E. (1967) Metal-insulator-SEMICONDUCTOR TRANSISTOR as a non-volatile storage element. International Electron Devices Meeting. (Abstracts). 58 [4] Frohman-Bentchkowsky, D. (1970) The metal-nitride-oxide-SILICON (MNOS) TRANSISTOR-characteristics and applications. Proceedings of IEEE. 58, 1207. [5] Yatsuda, Y., Hagiwara, T., Kondo, R., Minami, S., and Itoh, Y. (1979) N-channel Si-gate MNOS DEVICE for high speed EAROM. Proceedings 10th Conference in Solid State Devices. 11. [6] Suzuki, E., Hiraishi, H., Ishi, K., and Hayashi, Y. (1983) A low voltage alterable EEPROM with metal-oxide-nitride-oxide-SEMICONDUCTOR (MONOS) structure. IEEE Transactions on Electron Devices. ED-30, 122. [7] Frohman-Bentchkowsky, D. (1974) FAMOS-A new SEMICONDUCTOR charge storage DEVICE. Solid State ELECTRONICS. 17, 517. [8] Iizuka, H., Masuoka, F., Sato, T., and Ishikawa, M. (1976) ELECTRICally alterable avalanche-injection type MOS read-only MEMORY with stacked-gate structures. IEEE Transactions on Electron Devices. ED-23, 379. [9] Masuoka, F., Asano, M., Iwahashi, H., and Komuro, T. (1984) A new FLASH EEPROM cell using triple poly-Si TECHNOLOGY. IEEE IEDM Technical Digest. 464. [10] Yeargain, J. and Kuo, K. (1981) A high density floating gate EEPROM cell. IEEE IEDM Technical Digest. 24. [11] Guterman, D., Rimawi, I., Chiu, T., Halvorson, R., and McElroy, D. (1979) An electrically alterable nonvolatile MEMORY cell using a floating gate structure. IEEE Transactions on Electron Devices. ED-26, 576. [12] Lezlinger, M. and Snow, E. H. (1969) Fowler-Nordheim tunneling in THERMALly grown SiO2. Journal of Applied PHYSICS. 40, 278. [13] Tam, S., Ko, P., and Hu, C. (1984) Lucky-electron MODEL of channel hot-electron injection in MOSFET's. IEEE Transactions on Electron Devices. ED-31, 1116. [14] Takeda, E., Kume, H., Toyabe, T., and Asai, S. (1982) Submicrometer MOSFET structure for minimizing hot-carrier generation. IEEE Transactions on Electron Devices. ED-29, 611. [15] Shockley, W. (1961) Problems related to p-n junctions in SILICON. Solid-State ELECTRONICS. 2, 35. [16] Harari, E. (1978) Dielectric breakdown in electrically stressed thin films of THERMAL SiO2. Journal of Applied PHYSICS. 49, 2478. [17] Modelli, A. and Ricco, B. (1984) ELECTRIC field and current dependence of SiO2 intrinsic breakdown. IEEE IEDM Technical Digest. 148. [18] DiMaria, D. J. and Kerr, D. R. (1975) Interface effects and high conductivity in oxides grown from polycrystalline SILICON. Applied PHYSICS Letters. 27, 505. [19] Faraone, L. (1986) THERMAL SiO2 films on n+ polycrystalline SILICON: ELECTRICal conduction and breakdown. IEEE Transactions on Electron Devices. ED-33, 1785. [20] Mori, S., Kaneko, Y., Arai, N., Ohshima, Y., Araki, H., Narita, K., Sakagami, E., and Yoshikawa, K. (1990) Reliability study of thin inter-poly dielectrics for nonvolatile MEMORY application. Proceedings 1985 IEEE IRPS. 132. [21] Aminzadeh, M. (1988) Conduction and charge trapping in polySILICON nitride-oxide-SILICON structures under positive gate bias. IEEE Transactions on Electron Devices. ED-35, 205. [22] Shiner, R. E. (1980) Data retention in EPROMs. Proceedings IRPS. 238. [23] Mielke, N. (1983) New EPROM data-loss mechanisms. Proceedings IRPS. 106. [24] Verma, G. and Mielke, N. (1988) Reliability aspects of ETOX based FLASH memories. IRPS Proceedings, 158 |
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| 11楼： | >>参与讨论 |
| 作者： HIGHWAY 于 2005/12/24 21:34:00 发布：
不错,辛苦了 |
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| 12楼： | >>参与讨论 |
| 作者： sjb21ic 于 2005/12/25 14:09:00 发布：
盼望有更多的关于MEMORY的介绍 谢谢 |
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| 13楼： | >>参与讨论 |
| 作者： ljq0746 于 2005/12/27 23:09:00 发布：
请求设计自动拔打每一个用户的电话号码的电话机 现在在农村收电话费都是每个月到收电话费的时候一家一家打电话去告知别人要来交电话费呢，这样做比较麻烦。而且需要很多的时间，也比较麻，用电脑去做成本又太高呢，这样农村里代收员又用不起来。如果能设一种电路，能自动拔打每一个用户的电话号码，再有点语音提示就好呢， 请求各位帮帮忙，给我一些指导，我是农村收电话费的。不懂得这些电器电路。 我的QQ是：258118704 |
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| 14楼： | >>参与讨论 |
| 作者： xinglanp 于 2006/1/17 20:25:00 发布：
谢谢了，辛苦了！ |
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| 15楼： | >>参与讨论 |
| 作者： enddy 于 2006/1/19 9:15:00 发布：
文章很不错！！ 文章真的很不错，感谢楼主！顺便问一下，有没有NAND型和NOR型FLASH的具体资料，本人想了解一下！ |
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| 16楼： | >>参与讨论 |
| 作者： tomhe666 于 2006/1/21 0:21:00 发布：
为什么偶看不到 |
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| 17楼： | >>参与讨论 |
| 作者： iC921 于 2006/1/31 0:37:00 发布：
得好好看看 |
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| 18楼： | >>参与讨论 |
| 作者： iC921 于 2006/1/31 0:40:00 发布：
原作书名不妨给出来吧 |
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| 19楼： | >>参与讨论 |
| 作者： iC921 于 2006/1/31 0:53:00 发布：
有点“麻烦”：相当于两个作者 全面理解非易失存储器(FLASH,EPROM,EEPROM) --页面标题 -------------------------------------------------------------------------------- [日期：2006-1-3 15:59:08] 来源：21ICBBS 作者：code631 客人: 0 看到很多朋友问及非易失存储器的问题，手头有一份很好的材料，于是就有翻译成中文给大家讨论的念头，希望能给大家一些帮助。 版权申明： 该文章为翻译作品 原作者：Jitu J.Makwana, Dr.Dieter K.Schroder 翻译者：GongYi（INFINEON TECHNOLOGIES, MEMORY development center） email: code631@gmail.com 转贴请注明以上信息，谢谢合作。 ------------------------------------------------- http://www.18ic.com/Html/memory/2006010331.html 他们是［本站主题: 推广非日产器件及无日产器件的设计方案］的 http://www.18ic.com/html/memory/2006010331.html |
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| 20楼： | >>参与讨论 |
| 作者： iC921 于 2006/1/31 1:00:00 发布：
部分原文 A Nonvolatile MEMORY OverviewBy Jitu J. Makwana, Dr. Dieter K. Schroder*A Nonvolatile MEMORY Overview Jitu J. Makwana, Dr. Dieter K. Schroder* E-mail: j.makwana@worldnet.att.net, *schroder@asu.edu This paper presents a basic nonvolatile MEMORY (NVM) overview. Section I begins with the introduction including a brief background of NVM's and the common terms used in the MEMORY industry. The DESCRIPTION and explanation of how an NVM is programmed (adding electrons) using hot-carrier injection is covered in section II. Section III covers the erasing or removing of electrons from floating gates of NVM's. A brief mechanism of Fowler-Nordheim tunneling is covered. Section IV introduces the MODEL that can be used to predict the NVM PROGRAMMING characteristics. The hot-carrier injection MODEL addressed is the "Lucky Electron" MODEL. Section V covers the reliability aspects of NVM's. The common reliability issues an NVM encounters are the data retention, endurance, and disturbs. KEY WORDS: nonvolatile, MEMORY, hot-carrier injection, tunneling, reliability, retention, MEMORY disturbs, EPROM, FLASH EEPROM I. INTRODUCTION MEMORY can be split into two main categories: volatile and nonvolatile. Volatile MEMORY loses any data as soon as the SYSTEM is turned off; it requires constant POWER to remain viable. Most types of random access MEMORY (RAM) fall into this category. Nonvolatile MEMORY does not lose its data when the SYSTEM or DEVICE is turned off. A nonvolatile MEMORY (NVM) DEVICE is a MOS TRANSISTOR that has a source, a drain, an access or a CONTROL gate, and a floating gate. It is structurally different from a STANDARD MOSFET in its floating gate, which is electrically isolated, or "floating". Nonvolatile memories are subdivided into two main classes: floating gate and charge-trapping. Kahng and Sze proposed the first floating gate DEVICE in 1967 [1]. In this MEMORY, electrons were transferred from the floating gate to the substrate by tunneling through a 3 nm thin SILICON dioxide (SiO2) layer. Tunneling is the PROCESS by which an NVM can be either erased or programmed and is usually dominant in thin oxides of thicknesses less than 12 nm. Storage of the charge on the floating gate allows the threshold voltage (VT) to be electrically altered between a low and a high VALUE to represent LOGIC 0 and 1, respectively. In floating gate MEMORY DEVICEs, charge or data is stored in the floating gate and is retained when the POWER is removed. All floating gate memories have the same generic cell structure. They consist of a stacked gate MOS TRANSISTOR as shown in figure 1. The first gate is the floating gate that is buried within the gate oxide and the inter-polySILICON dielectric (IPD) beneath the CONTROL gate. The IPD isolates the floating gate and can be oxide or oxide-nitride-oxide, ONO. The SiO2 dielectric surrounding the TRANSISTOR serves as a protective layer from scratches and defects. The second gate is the CONTROL gate which is the external gate of the MEMORY TRANSISTOR. Floating gate DEVICEs are typically used in EPROM (Electrically Programmable Read ONLY MEMORY) and EEPROM's (Electrically Erasable and Programmable Read ONLY MEMORY). Figure 1. A typical floating gate MEMORY structure.  Charge-trapping DEVICEs were invented in 1967 [2] and were the first electrically alterable SEMICONDUCTOR DEVICEs. In charge-trapping MEMORY DEVICEs, charge or data is stored in the discrete nitride traps and is also retained when the POWER is removed. Charge-trapping DEVICEs are typically used in MNOS (METAL Nitride Oxide SILICON) [3], [4], SNOS (SILICON Nitride Oxide SEMICONDUCTOR) [5], and SONOS (SILICON Oxide Nitride Oxide SEMICONDUCTOR) [6]. Figure 2 shows a typical MNOS charge-trapping MEMORY structure. Figure 2. An MNOS MEMORY cell structure.  The charges in MNOS memories are injected from the channel region into the nitride by quantum MECHANICAL tunneling through an ultra-thin oxide (UTO) which is typically 1.5 - 3 nm. The first EPROM, a floating gate DEVICE, was developed using a heavily doped polySILICON (poly-Si) as the floating gate material known as the floating gate avalanche-injection MOS MEMORY (FAMOS) [7]. The gate oxide thickness was of the order of 100 nm to prevent weak spot or shorting path between the floating gate and the substrate. Charging of the EPROM was achieved by biasing the drain junction to avalanche breakdown where the electrons in the avalanche PLASMA were injected from the drain region into the floating gate. The FAMOS could ONLY be erased by ultraviolet (UV) or x-ray. The EPROM was perceived as a tool for SYSTEM prototyping before a design was committed to Read ONLY MEMORY (ROM). Today, one can obtain EPROM's in either a ceramic PACKAGE with a quartz window that allows for UV exposure or a plastic PACKAGE without a quartz window. These memories are known as one-time-programmable (OTP) EPROM's. OTP's are inexpensive, however, additional testing after assembly is not possible. EPROM's in ceramic PACKAGEs with a quartz window are expensive but do allow additional testing since the MEMORY can be erased using UV light. Although the 1970's saw the UV-erasable, electrically programmable memories become commercially successful, there was an ever-present attraction toward making the EPROM's electrically erasable, EEPROM. H. Iizuka et. al [8], proposed the first electrical erasing NVM known as the stacked gate avalanche-injection MOS (SAMOS) MEMORY. SAMOS MEMORY consisted of double poly-Si gates with an external CONTROL gate. The external CONTROL gate made electrical erasability possible and as a result improved the erasing efficiency. The EEPROM's basic approach with electrical means of restoring the charged floating gate to its original uncharged status replaced UV emission approach. Cheaper packaging and a greater ease of use were the first advantages of EEPROM's over their UV-erasable counterparts. The disadvantage of EEPROM's was the cell size that was two to three times the size of an EPROM cell that resulted in a larger die size. EEPROM cells consist of two TRANSISTORs, one, a floating gate TRANSISTOR and the other, a SELECT gate TRANSISTOR, as shown in figure 3. The SELECT gate TRANSISTOR is used to SELECT or deSELECT floating gate TRANSISTORs for PROGRAMMING or erasing. Die size was further increased to incorporate error correction circuitry or redundancy circuits. Figure 3. An EEPROM with SELECT gate TRANSISTOR.  During the 1980's, a novel nonvolatile MEMORY PRODUCT was introduced, referred to as FLASH EEPROM [9]. The first PRODUCTs were merely the result of adapting EPROM's in such a way that the cell could be erased electrically as well. These DEVICEs used hot-electron injection for PROGRAMMING and tunneling for erasing. This new genre of FLASH EEPROM's could not be erased by bytes but could ONLY be erased by the entire chip or large sections of the chip. Since the need to erase by bytes as in EEPROM's was no longer needed in FLASH EEPROM's, the SELECT TRANSISTOR was removed from the cell structure. Thus the FLASH EEPROM's were two to three times smaller than earlier EEPROM cells. The generic cell structure of a FLASH EEPROM is similar to a generic cell structure shown in figure 1. Below is a nomenclature or a list of MEMORY terms (not exhaustive) used in the literature, industry, and education fields:
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| 21楼： | >>参与讨论 |
| 作者： iC921 于 2006/1/31 1:03:00 发布：
续1 IIb. Hot-carrier Injection (HCI) NVM's can also be programmed by hot-carrier injection. The method of PROGRAMMING is by hot-electron injection for N-TYPE NVM's built on p-substrates and by hot hole injection for p-type NVM's built on n-substrates. Hot-hole injection is very slow due to the hole mass as well as the Si-SiO2 energy barrier of 4.7 eV for holes, which is why all NVM's manufactured today are N-TYPE on p-substrates. The MEMORY cell is programmed by charging the floating gate via the injection of hot-electrons from the drains pinch-off region. The hot-electrons get their energy from the voltage applied to the drain (Vd) of the MEMORY cell. They are accelerated by the lateral ELECTRIC field (Elat) along the channel into even higher fields surrounding the drain depletion region. Once these electrons gain sufficient energy they surmount the energy barrier of 3.2 eV between the SILICON substrate and the SILICON diELECTRIC layer or gate oxide. With positive Vd and channel voltages, electrons injected into the oxide of an n-channel MEMORY cells return to the substrate unless a high positive Vcg is applied to pull the electrons toward the floating gate. The energy band structure for NVM PROGRAMMING by hot-electron injection is shown in figure 7. Figure 7. Energy band diagram of a floating gate MEMORY during PROGRAMMING by hot-electron injection.  As the floating gate becomes fully charged, the gate current (Ig) is reduced to almost zero because the oxide ELECTRIC field (Eox) (in the beginning of the injection PROCESS Eox was attractive to the electrons) is now repulsive to the electrons. In general, to the first order, Vcg increases the charge on the floating gate while Vd affects the PROGRAMMING speed. Figure 8 shows a cross-section of an NVM with hot-electron injection PROGRAMMING. Vcg and Vd are at positive potential of 15 V and 10 V respectively while Vs and Vsub are at ground potential. The p-well is also shown, as it is the PROCESS needed to separate n-channel and p-channel MOS transistors from NVM's DEVICEs. Figure 8. Hot-electron injection mechanism for PROGRAMMING in NVM's.  III. BASIC ERASING MECHANISMS Section II covered the two PROGRAMMING schemes, namely, FN tunneling and hot-electron injection. In order to reprogram an NVM, it first has to be erased. This section will cover the erasing schemes commonly employed in the industry. The electrons that are injected into the floating gate are trapped by the high gate to oxide energy barrier of 3.2 eV. Since the potential-energy barrier at the oxide-SILICON interface is greater than 3.0 eV, the rate of spontaneous emission of electrons from the oxide over this barrier is negligibly small. The net negative charge which remains on the floating gate shifts the VT to a positive VALUE. There are two methods of erasing or removing charge:
IIIa. UV Emission Referring to figure 9, electrons gain enough energy acquired from the UV radiation to surmount the energy barrier from the floating gate to either the CONTROL gate or to the substrate, which reduces the VT. The typical time it takes to change the VT from programmed state to neutral or erased state is 10 minutes. Figure 9. Energy band diagram of UV erase of an NVM.  IIIb. FN Tunneling FN tunneling can also be used to erase an NVM. One of the methods is by applying a large negative voltage at the CONTROL gate. The energy band structure will be influenced as shown in figure 10. The applied Vcg creates the ELECTRIC field resulting in a potential barrier. This barrier provides a path for the electrons to tunnel from the floating gate to the substrate through the thin gate oxide. Figure 10. Energy band diagram of a floating gate MEMORY during erasing by FN tunneling.  Figure 11a and 11b shows two choices to erase a FLASH EEPROM. For uniform tunneling, a large negative Vcg is applied while for drain-side tunneling method, both a negative Vcg and a positive Vd are applied. Figure 11a. Uniform tunneling to erase FLASH EEPROM.  Figure 11b. Drain-side tunneling to erase FLASH EEPROM.  In general, uniform tunneling is slower that drain-side tunneling, but, drain-side tunneling tends to cause reliability issues. The reliability issue is the gate oxide damage that occurs near the drain since a small area is bombarded by electrons and that the tunneling current density as a result of small area is higher. IV. HOT-CARRIER INJECTION MODEL One of the methods of PROGRAMMING an EPROM or a FLASH EEPROM is by channel hot-electron injection (CHE) where hot-electrons are generated in the high field region between the pinched-off channel and drain. Electrons with sufficient energy are injected across the oxide to the floating gate, thereby PROGRAMMING the DEVICE (increasing the threshold voltage to positive VALUE, VT). This PROCESS of PROGRAMMING is slow due to the injection efficiency, which is dependent on three probability events. The hot-carrier injection mechanism gives rise to impact ionization at the drain, by which both minority (electrons) and majority (holes) carriers are generated. The highly energetic holes are normally collected at the substrate contact and form the substrate current (Isub) while the minority carriers are collected at the drain and forms the drain current (Ids). If the oxide ELECTRIC field (Eox) favors injection, these carriers are injected over the energy barrier (fb) of the gate oxide and gives rise to hot-carrier injection gate current (Ig). In the case of floating gate memories, these electrons change the charge content of the floating gate. There are two MODELs that can be used to describe the gate current due to hot-electron injection. The two MODELs are the lucky-electron MODEL [13] and the effective electron temperature MODEL [14]. IVa. Lucky-electron MODEL and Threshold Programmed VT The lucky-electron approach of MODELing the hot-electron distribution was originated by Shockley [15]. Conceptually, the lucky-electron MODEL can be described as follows. In order for hot-electrons to reach the gate, the hot-electrons must gain sufficient kinetic energy from the lateral channel field (Elat) and have its momentum redirected towards the Si-SiO2 interface in order to surmount the SiO2 energy barrier (fb). Figure 12 shows the concepts involved in the lucky-electron MODEL. The three events involved in the lucky-electron MODEL are:
Figure 12. The three PROCESSes in the lucky-electron injection MODEL. 
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and is defined as the probability of an electron having enough normal momentum to surmount the Si-SiO2 potential barrier height.| 22楼： | >>参与讨论 | ||||||||||||
| 作者： iC921 于 2006/1/31 1:07:00 发布：
续2 V. NONVOLATILE MEMORY RELIABILITY Nonvolatile MEMORY cells have some important functional characteristics, which are used to evaluate the performance of the cell. These characteristics are divided into two main classes, namely endurance and retention. In order to understand endurance and retention characteristics, it is imperative to know some of the fundamentals associated with gate oxide and interpolysilicon diELECTRIC, IPD, integrity. Although traps are the storage sites in MNOS, SNOS, and SONOS memories, they constitute the very means that LEAD to reliability failures in EPROM's, EEPROM's, and FLASH EEPROM's. The gate oxide and IPD quality can affect endurance and retention. The primary failure mechanism of the gate oxide pertains to oxide breakdown and trap-up due to high injection ELECTRIC field STRESSing during hot-electron injection or FN tunneling. It was suggested that oxide defects and broken Si-O bonds serve as trapping centers [16] for positive (holes) charge. Oxide breakdown occurs after a fixed amount of charge per unit area (Qbd) has been injected and has been shown to be a function of applied ELECTRIC field [17]. Qbd is an industry STANDARD ELECTRICal TEST used to measure the quality of the oxide with higher Qbd (GOOD oxide quality) as the desired goal. Trap-up is defined as the trapping of electrons in the oxide during PROGRAMMING/writing operations. These trapped charges change the injection fields and thus, the amount of charge transferred to and from the floating gate during PROGRAMMING. As described earlier, one of the components of a nonvolatile MEMORY cell structure is the IPD. In nonvolatile memories, IPD is used to isolate the floating gate from other electrodes (CONTROL gate, source, drain, and the substrate) and hence, should be defect-free to prevent charge leakage from the floating gate. Since the floating gate is a poly-Si layer, it is commonly oxidized during the IPD growth PROCESS. The oxidation of poly-Si layer modifies the surface topology due to enhanced oxidation at the grain boundaries of the poly-Si, forming interface protuberances and inclusions [18]. The surface nonuniformities causes ELECTRIC field enhancement resulting in higher leakage currents, which is a drawback for an insulating IPD. Figure 14 shows a CIRCUIT diagram of the effects of nonuniformities with respect to ELECTRIC field enhancement. Other factors that influences the IPD quality are the doping of the floating gate poly-Si layer and the temperature of both the poly-Si deposition and the oxidation [19]. Multiple diELECTRIC stacks such as the oxide-nitride-oxide (ONO) are now commonly used as IPD's for lower leakage due to lower defect densities and higher ELECTRIC field properties [20]. The lower leakage currents are achieved due to the fact that the electrons that have leaked from the floating gate gets trapped in the oxide-nitride interface which builds an ELECTRIC field that opposes further charge loss [21]. Typical thicknesses of the ONO stack are 5 - 10 nm, 20 nm, and 3 nm for the bottom oxide, nitride, and the top oxide respectively. The bottom oxide is the oxide above the floating gate while the top oxide is the oxide beneath the CONTROL gate. Figure 14. IPD leakage current due to nonuniformities.  Va. Endurance Characteristics The endurance characteristics give the MEMORY threshold voltage window, which is the difference between the threshold voltages in the programmed/written state and the erased states, as a function of the NUMBER of PROGRAMMING cycles, as shown in figure 15. Nonvolatile memories can be programmed and erased frequently at the expense of introducing permanent gate oxide damage such as oxide breakdown and trap-up. This implies that the total NUMBER of program operations is limited; for example, most commercially available EEPROM products are guaranteed to withstand 106 PROGRAMMING cycles. The damaging of the MEMORY cell during cycling is normally referred to as "degradation" and the NUMBER of cycles the MEMORY can withstand is called "endurance". Threshold voltage window closure occurs when the threshold voltage difference between the programmed and erased states cannot be distinguished. The phenomenon of window closure has been attributed to trapping of injected electrons in the gate oxide due to pre-existing electron traps. There is also evidence of trap generation during PROGRAMMING and erasing due to high ELECTRIC field STRESS (Einj). It is thus important to have high quality gate oxides that can endure constant electron STRESS during hot-electron injection or FN tunneling. Figure 15. Typical EEPROM cell threshold voltage window versus log cycles.  Vb. Retention Characteristics When a nonvolatile MEMORY cell can no longer hold the charge in the floating gate, it is said to have affected its retention capability. Retention is a measure of the time that a nonvolatile MEMORY cell can retain the charge whether it is powered or unpowered. In floating gate memories, the stored charge can leak away from the floating gate through the gate oxide or through the IPD. This leakage caused by mobile ions and oxide defects, result in a shift of the threshold voltage of the MEMORY cell. Different charge loss mechanisms have been described [22], [23], namely, charge loss due to thermionic emission, charge loss due to electron detrapping, and charge loss due to contamination such as positive mobile ions. To improve the retention characteristics of the MEMORY cell, various improvements to the quality of the gate oxide and IPD becomes very important. Retention can be quantified by measuring or estimating the time it takes for the floating gate to discharge when it is intended to KEEP the information stored. When charge loss occurs, a shift in the VT of the MEMORY cell occurs according to equation 8.  (8)where dQFG, CFG, and dVT are the floating gate charge loss, floating gate capacitance, and the floating gate VT shift respectively. Equation 9 shows the EVALUATION of the NUMBER of electrons lost and equation 10 shows how the NUMBER of electrons lost is related to leakage current, ILeakage and retention time, dt.  (9) (10)For a typical CFG of 30 fF and a VT shift of 3 V, the # of electrons lost from the floating gate to CONTROL gate is 5.6x105. Table 1 shows the retention time, dt, for various ILeakage associated with a loss of 5.6x105 electrons or 3 V VT shift.
Table 1. Retention time as function of ILeakage. Table 1 shows that it would take 10 years for an NVM to loose charge equivalent to 3 V shift for a leakage current of 2.85x10-22 A. Vc. MEMORY Disturbs Widespread use of nonvolatile memories in production systems requires data retention for ten years or more. A typical MEMORY array undergoes STRESSes that arise during PROGRAMMING and erasing commonly |
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| 23楼： | >>参与讨论 |
| 作者： davidhu 于 2006/2/5 21:48:00 发布：
请教！ FLASH ROM寿命终了后是表现为一个RAM还是根本就不能读写了？ |
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| 24楼： | >>参与讨论 |
| 作者： davidhu 于 2006/2/5 21:49:00 发布：
请教！ FLASH ROM 读写次数超过其寿命后是表现为相RAM一样还是根本就不能读写了？ |
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| 25楼： | >>参与讨论 |
| 作者： davidli88 于 2006/2/18 22:02:00 发布：
真是好人呀 |
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| 26楼： | >>参与讨论 |
| 作者： berryfan 于 2006/3/1 12:48:00 发布：
强 感谢楼主，不过在下佩服英语水平。 |
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| 27楼： | >>参与讨论 |
| 作者： cathymm 于 2006/3/1 21:47:00 发布：
非常好 谢谢 |
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| 28楼： | >>参与讨论 |
| 作者： jiang.xx 于 2006/3/7 14:01:00 发布：
能告诉我NOR 与NAND FLASH之间的差别吗? 我想了解以上FLASH之间的差别,如何在DATASHEET里面分别? 多谢了! |
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| 29楼： | >>参与讨论 |
| 作者： code631 于 2006/3/7 21:13:00 发布：
nand 和 nor nand nor是指存储器array的排列方式，nand架构的存储单元排列为串行排列，nor为并行。nor的寻址速度快，(SINGLE cells addressable)而nand比较慢。目前市场上nand的占有率绝对占优。单片容量超过1g的基本都是nand的天下。 |
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| 30楼： | >>参与讨论 |
| 作者： sagegao 于 2006/3/10 11:12:00 发布：
牛！ |
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| 31楼： | >>参与讨论 |
| 作者： 远看 于 2006/3/12 10:06:00 发布：
收藏了,谢谢 |
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| 32楼： | >>参与讨论 |
| 作者： zzh749 于 2006/3/12 23:09:00 发布：
？！ 顶！！ |
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| 33楼： | >>参与讨论 |
| 作者： sdaniu 于 2006/3/22 14:12:00 发布：
来欣赏了 再次谢过了。 要好好读一下。呵呵 |
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| 34楼： | >>参与讨论 |
| 作者： CR333 于 2006/3/29 13:39:00 发布：
见不到材料 见不到材料，如有电子版的，请发送到邮箱：lmemail@eyou.com 多谢！ |
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| 35楼： | >>参与讨论 |
| 作者： A杜 于 2006/3/30 21:55:00 发布：
顶 果然是精华帖！ |
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| 36楼： | >>参与讨论 |
| 作者： A杜 于 2006/3/30 22:18:00 发布：
顶 顶！ |
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| 37楼： | >>参与讨论 |
| 作者： flyoxy 于 2006/4/1 21:20:00 发布：
正好学习一把 |
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| 38楼： | >>参与讨论 |
| 作者： code631 于 2006/4/4 19:31:00 发布：
版下载不了，21ic 的ftp也用不了，真是郁闷！ |
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| 39楼： | >>参与讨论 |
| 作者： yzqok 于 2006/4/8 16:42:00 发布：
真是好资料! |
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| 40楼： | >>参与讨论 |
| 作者： smaltdog 于 2006/4/12 10:00:00 发布：
好东西大家一起分享! 近日发现一个特别棒的网站，不仅可以发布供求信息，还可以查阅很多电子专业资料，大家不妨去看看！www.elecunite.com |
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| 41楼： | >>参与讨论 |
| 作者： cherrychip 于 2006/4/21 0:27:00 发布：
盖房的不用管造砖的,造砖的是否还要学烧窑的?哈哈 |
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| 42楼： | >>参与讨论 |
| 作者： no2 于 2006/4/24 9:48:00 发布：
好东西 顶一下。 不过我好像不能下载PDF文件，只好自己整理LZ的文章了。 |
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| 43楼： | >>参与讨论 |
| 作者： shq8144849 于 2006/5/25 19:16:00 发布：
不错不错，很专业的哦。 不错不错，很专业的哦。 |
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| 44楼： | >>参与讨论 |
| 作者： loosing 于 2006/5/30 14:58:00 发布：
下载在哪里？ |
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| 45楼： | >>参与讨论 |
| 作者： liu654 于 2006/6/15 13:51:00 发布：
为什么提示已经删除或者过期啊 为什么提示已经删除或者过期啊，还能再下吗？ |
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| 46楼： | >>参与讨论 |
| 作者： cherrychip 于 2006/6/27 20:12:00 发布：
NAND FLASH芯片综合测试板(照片) NAND FLASH芯片综合测试板中科院电子所北京科电恒光科技发展公司研制，自动识别多个品牌的NAND FLASH芯片的品牌名称、原厂型号、容量，可以作删除操作并同时测试坏块数量，对于0块损坏的特别提示，最具特点的是可以测试芯片的写入速度，精度达到10uS，准确判断被测试芯片的等级。 本测试板可以在数秒钟内完成芯片删除并显示坏块数量，可以在瞬间识别出没有LOGO的白片的原厂品牌名称和型号容量，是科研、量产、采购判断芯片优劣，识别白片和假冒打磨片的有利工具。可以扩展1-7个适配器板，实现多片同时测试、删除、COPY。 资料下载:http://www.cherrychip.net/FLASH-T1.pdf * - 本贴最后修改时间：2006-7-15 14:02:24 修改者：cherrychip
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| 47楼： | >>参与讨论 |
| 作者： 王彦 于 2006/7/14 10:04:00 发布：
不错 没看到啊 |
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| 48楼： | >>参与讨论 |
| 作者： nichao99 于 2006/7/18 11:42:00 发布：
不错不错 |
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| 49楼： | >>参与讨论 |
| 作者： gxpa1 于 2006/9/12 9:58:00 发布：
在哪啊 |
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| 50楼： | >>参与讨论 |
| 作者： 汇展科技 于 2006/9/20 10:19:00 发布：
樓主辛苦了 樓主辛苦了 |
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| 51楼： | >>参与讨论 |
| 作者： honeir 于 2006/9/29 19:07:00 发布：
Thanks a lot! 楼主能否发一份给我，最好连e文的一块发给我！ 谢谢！ |
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| 52楼： | >>参与讨论 |
| 作者： bjjtyl 于 2006/10/14 22:07:00 发布：
能否将你的资料给我发一份？ 能否将你的资料给我发一份？谢谢，我也学习学习。 董迎春 |
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| 53楼： | >>参与讨论 |
| 作者： shaohaigod 于 2006/10/30 18:07:00 发布：
给我一份吧 给我一份吧 shaohaigod@163.com |
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| 54楼： | >>参与讨论 |
| 作者： micheal123 于 2006/11/9 14:20:00 发布：
thanks |
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| 55楼： | >>参与讨论 |
| 作者： gliu 于 2006/11/15 17:02:00 发布：
3Q 如果楼主很热心的话,那就给兄弟我发一个吧 lg_vagrant@163.com |
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| 56楼： | >>参与讨论 |
| 作者： lhmail3 于 2006/12/11 14:32:00 发布：
好啊 好啊 |
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| 57楼： | >>参与讨论 |
| 作者： qiang0726 于 2007/1/9 14:21:00 发布：
谢谢 |
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| 58楼： | >>参与讨论 |
| 作者： kings8105 于 2007/1/27 12:58:00 发布：
需要! 呵呵~~ 我也需要一份 我的E-MAIL:kings8105@hotmail.com 谢谢! |
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| 59楼： | >>参与讨论 |
| 作者： 9805210005 于 2007/2/28 17:01:00 发布：
我需要一个 我好需要啊wang.zi.ling@163.com 多谢了 |
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| 60楼： | >>参与讨论 |
| 作者： devil110 于 2007/3/7 10:22:00 发布：
现有没有哦! 还有的话给我一份哦!:devil5_angel!163.com 谢谢了! |
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| 61楼： | >>参与讨论 |
| 作者： ha_exit 于 2007/3/13 21:02:00 发布：
好东西 请问，怎么看不到下载链接啊 |
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| 62楼： | >>参与讨论 |
| 作者： 疯狂的闪电 于 2007/3/20 21:55:00 发布：
在哪下载？ 在哪下载？ |
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| 63楼： | >>参与讨论 |
| 作者： xuqinglei 于 2007/3/26 16:39:00 发布：
where? 那呢？ |
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| 64楼： | >>参与讨论 |
| 作者： budoudou 于 2007/4/19 9:56:00 发布：
好啊 我也想要一份！！谢谢呀！！ |
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| 65楼： | >>参与讨论 |
| 作者： phton 于 2007/5/10 16:38:00 发布：
LZ辛苦 |
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| 66楼： | >>参与讨论 |
| 作者： kathleen 于 2008/10/5 22:06:47 发布：
楼主，可否给我一份啊，谢谢哦 |
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