- 200 MHz internal clock rate
- 14-bit data path
- Excellent dynamic performance: 80 dB SFDR @ 65 MHz (±100 kHz) AOUT
- 4× to 20× programmable reference clock multiplier
- Reference clock multiplier PLL lock detect indicator
- Internal 32-bit quadrature DDS
- FSK capability
|
- 8-bit output amplitude control
- Single-pin power-down function
- Four programmable, pin-selectable
signal profiles
- SIN(x)/x correction (inverse
SINC function)
- Simplified control interface
10 MHz serial, 2-wire or 3-wire
SPI®-compatible |
