MM74HC595 8-Bit Shift Registers with Output Latches
September 1983
Revised February 1999
MM74HC595
8-Bit Shift Registers with Output Latches
General Description
The MM74HC595 high speed shift register utilizes
advanced silicon-gate CMOS technology. This device pos-
sesses the high noise immunity and low power consump-
tion of standard CMOS integrated circuits, as well as the
ability to drive 15 LS-TTL loads.
This device contains an 8-bit serial-in, parallel-out shift reg-
ister that feeds an 8-bit D-type storage register. The stor-
age register has 8 3-STATE outputs. Separate clocks are
provided for both the shift register and the storage register.
The shift register has a direct-overriding clear, serial input,
and serial output (standard) pins for cascading. Both the
shift register and storage register use positive-edge trig-
gered clocks. If both clocks are connected together, the
shift register state will always be one clock pulse ahead of
the storage register.
The 74HC logic family is speed, function, and pin-out com-
patible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to V
CC
and ground.
Features
s
Low quiescent current: 80
碌A
maximum (74HC Series)
s
Low input current: 1
碌A
maximum
s
8-bit serial-in, parallel-out shift register with storage
s
Wide operating voltage range: 2V鈥?V
s
Cascadable
s
Shift register has direct clear
s
Guaranteed shift frequency: DC to 30 MHz
Ordering Code:
Order Number
MM74HC595M
MM74HC595WM
MM74HC595SJ
MM74HC595MTC
MM74HC595N
Package Number
M16A
M16B
M16D
MTC16
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150鈥?Narrow
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300鈥?Wide
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300鈥?Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Truth Table
RCK
X
X
SCK
X
X
SCLR
X
L
G
H
L
Function
Q
A
thru Q
H
=
3-STATE
Shift Register cleared
Q
H
=
0
X
鈫?/div>
H
L
Shift Register clocked
Q
N
=
Q
n-1
, Q
0
=
SER
鈫?/div>
X
H
L
Contents of Shift
Register transferred
to output latches
Top View
漏 1999 Fairchild Semiconductor Corporation
DS005342.prf
www.fairchildsemi.com
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