特性

500 ps Typical Propagation Delay

Maximum Frequency > 2.1 Ghz Typical

Fully Differential Internally

Advanced High Band Output Swing of 400 mV

Transfer Gain: 1.0 mV/Degree at 1.4 GHz, 1.2 mV/Degree at 1.0 GHz

Rise and Fall Time: 100 ps Typical

The 100 Series Contains Temperature Compensation

PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V

NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V

Open Input Default State

Pb-Free Packages are Available

描述

The MC100EP140 is a three state phase frequency-detector intended for phase-locked loop applications which require a minimum amount of phase and frequency difference at lock. Since the part is designed with fully differential gates, the noise is reduced throughout the circuit, especially at high speeds. The basic operation of a Phase/Frequency Detector (PFD) is to "compare" an incoming signal (feedback) to a set reference signal. When the Reference (R) and Feedback (FB) inputs are unequal in frequency and/or phase, the differential UP (U) and DOWN (D) outputs will provide pulse streams which when subtracted and integrated provide an error voltage for control of a VCO.

The device is packaged in a small outline, surface mount 8-lead SOIC package. The output of the EP140 is 400 mV, which allows faster switching time and greater bandwidth. This device can also be used in +3.3 V systems. For proper operation, the input edge rate of the R and FB inputs should be less than 5 ns.

More information on Phase Lock Loop operation and application can be found in AND8040.