AD9861-50EB Datasheet

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AD9861-50EB
PDF描述：
Mixed-Signal Front-End (MxFE⑩) Baseband Transceiver for Bro...
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Mixed-Signal Front-End (MxFE

鈩?/div>

) Baseband

Transceiver for Broadband Applications

AD9861

FEATURES

Receive path includes dual 10-bit analog-to-digital

converters with internal or external reference, 50 MSPS

and 80 MSPS versions

Transmit path includes dual 10-bit, 200 MSPS digital-to-

analog converters with 1脳, 2脳, or 4脳 interpolation and

programmable gain control

Internal clock distribution block includes a programmable

phase-locked loop and timing generation circuitry,

allowing single-reference clock operation

20-pin flexible I/O data interface allows various interleaved

or noninterleaved data transfers in half-duplex mode and

interleaved data transfers in full-duplex mode

Configurable through register programmability or

optionally limited programmability through mode pins

Independent Rx and Tx power-down control pins

64-lead LFCSP package (9 mm 脳 9 mm footprint)

3 configurable auxiliary converter pins

VIN+A

ADC

VIN鈥揂

VIN+B

ADC

VIN鈥揃

I/O

INTERFACE

CONFIGURATION

BLOCK

DATA

MUX

AND

LATCH

Rx DATA

FUNCTIONAL BLOCK DIAGRAM

I/O

INTERFACE

CONTROL

FLEXIBLE

I/O BUS

[0:19]

LOW-PASS

INTERPOLATION

FILTER

IOUT+A

DAC

IOUT鈥揂

IOUT+B

DAC

IOUT鈥揃

DATA

LATCH

AND

DEMUX

Tx DATA

AUX

ADC

AUX

DAC

ADC CLOCK

AUX

DAC

DAC CLOCK

AUX

ADC

PLL

CLKIN

APPLICATIONS

Broadband access

Broadband LAN

Communications (modems)

AD9861

AUX

DAC

03606-0-001

Figure 1.

GENERAL DESCRIPTION

The AD9861 is a member of the MxFE family鈥攁 group of

integrated converters for the communications market. The

AD9861 integrates dual 10-bit analog-to-digital converters

(ADC) and dual 10-bit digital-to-analog converters (TxDAC庐).

Two speed grades are available, -50 and -80. The -50 is opti-

mized for ADC sampling of 50 MSPS and less, while the -80 is

optimized for ADC sample rates between 50 MSPS and 80 MSPS.

The dual TxDACs operate at speeds up to 200 MHz and

include a bypassable 2脳 or 4脳 interpolation filter. Three

auxiliary converters are also available to provide required

system level control voltages or to monitor system signals. The

AD9861 is optimized for high performance, low power, small

form factor, and to provide a cost-effective solution for the

broadband communication market.

The AD9861 uses a single input clock pin (CLKIN) to generate

all system clocks. The ADC and TxDAC clocks are generated

within a timing generation block that provides user programma-

ble options such as divide circuits, PLL multipliers, and switches.

A flexible, bidirectional 20-bit I/O bus accommodates a variety

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

of custom digital back ends or open market DSPs.

In half-duplex systems, the interface supports 20-bit parallel

transfers or 10-bit interleaved transfers. In full-duplex systems,

the interface supports an interleaved 10-bit ADC bus and an

interleaved 10-bit TxDAC bus. The flexible I/O bus reduces pin

count and, therefore, reduces the required package size on the

AD9861 and the device to which it connects.

The AD9861 can use either mode pins or a serial program-

mable interface (SPI) to configure the interface bus, operate the

ADC in a low power mode, configure the TxDAC interpolation

rate, and control ADC and TxDAC power-down. The SPI

provides more programmable options for both the TxDAC path

(for example, coarse and fine gain control and offset control for

channel matching) and the ADC path (for example, the internal

duty cycle stabilizer, and twos complement data format).

The AD9861 is packaged in a 64-lead LFCSP (low profile, fine

pitched, chip scale package). The 64-lead LFCSP footprint is

only 9 mm 脳 9 mm, and is less than 0.9 mm high, fitting into

tightly spaced applications such as PCMCIA cards

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.326.8703

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