DM74LS240 鈥?DM74LS241 Octal 3-STATE Buffer/Line Driver/Line Receiver
August 1986
Revised March 2000
DM74LS240 鈥?DM74LS241
Octal 3-STATE Buffer/Line Driver/Line Receiver
General Description
These buffers/line drivers are designed to improve both the
performance and PC board density of 3-STATE buffers/
drivers employed as memory-address drivers, clock driv-
ers, and bus-oriented transmitters/receivers. Featuring
400 mV of hysteresis at each low current PNP data line
input, they provide improved noise rejection and high
fanout outputs and can be used to drive terminated lines
down to 133鈩?
Features
s
3-STATE outputs drive bus lines directly
s
PNP inputs reduce DC loading on bus lines
s
Hysteresis at data inputs improves noise margins
s
Typical I
OL
(sink current)
24 mA
s
Typical I
OH
(source current)
鈭?5
mA
s
Typical propagation delay times
Inverting
Noninverting
10.5 ns
12 ns
s
Typical enable/disable time 18 ns
s
Typical power dissipation (enabled)
Inverting
Noninverting
130 mW
135 mW
Ordering Code:
Order Number
DM74LS240WM
DM74LS240SJ
DM74LS240N
DM74LS241WM
DM74LS241N
Package Number
M20B
M20D
N20A
M20B
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagrams
DM74LS240
DM74LS241
漏 2000 Fairchild Semiconductor Corporation
DS006411
www.fairchildsemi.com
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