庐
ISL6524A
Data Sheet
April 8, 2005
FN9064.1
VRM8.5 PWM and Triple Linear Power
System Controller
The ISL6524A provides the power control and protection for
four output voltages in high-performance microprocessor and
computer applications. The IC integrates one PWM controller
and three linear controllers, as well as the monitoring and
protection functions into a 28-pin SOIC package. The PWM
controller regulates the microprocessor core voltage with a
synchronous-rectified buck converter. One linear controller
supplies the computer system鈥檚 AGTL+ 1.2V bus power. The
other two linear controllers regulate power for the 1.5V AGP
bus and the 1.8V power for the chipset core voltage and/or
cache memory circuits.
The ISL6524A includes an Intel VRM8.5 compatible, TTL
5-input digital-to-analog converter (DAC) that adjusts the
microprocessor core-targeted PWM output voltage from
1.050V to 1.825V in 25mV steps. The precision reference and
voltage-mode control provide
卤1%
static regulation. The linear
regulators use external N-channel MOSFETs or bipolar NPN
pass transistors to provide fixed output voltages of 1.2V
卤3%
(V
OUT2
), 1.5V
卤3%
(V
OUT3
) and 1.8V
卤3%
(V
OUT4
).
The ISL6524A monitors all the output voltages. A delayed-
rising VTT (V
OUT2
output) Power Good signal is issued
before the core PWM starts to ramp up. Another system
Power Good signal is issued when the core is within
卤10%
of
the DAC setting and all other outputs are above their under-
voltage levels. Additional built-in over-voltage protection for
the core output uses the lower MOSFET to prevent output
voltages above 115% of the DAC setting. The PWM
controllers鈥?over-current function monitors the output current
by using the voltage drop across the upper MOSFET鈥檚
r
DS(ON)
, eliminating the need for a current sensing resistor.
Features
鈥?Provides 4 Regulated Voltages
- Microprocessor Core, AGTL+ Bus, AGP Bus Power,
and North/South Bridge Core
鈥?Drives N-Channel MOSFETs
鈥?Linear Regulator Drives Compatible with both MOSFET
and Bipolar Series Pass Transistors
鈥?Simple Single-Loop Control Design
- Voltage-Mode PWM Control
鈥?Fast PWM Converter Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Ratio
鈥?Excellent Output Voltage Regulation
- Core PWM Output:
卤1%
Over Temperature
- All Other Outputs:
卤3%
Over Temperature
鈥?VRM8.5 TTL-Compatible 5-Bit DAC Microprocessor Core
Output Voltage Selection
- Wide Range - 1.050V to 1.825V
鈥?Power-Good Output Voltage Monitors
- Separate delayed VTT Power Good
鈥?Over-Voltage and Over-Current Fault Monitors
- Switching Regulator Doesn鈥檛 Require Extra Current
Sensing Element, Uses MOSFET鈥檚 r
DS(ON)
鈥?Small Converter Size
- Constant Frequency Operation
- 200kHz Internal Oscillator
鈥?Pb-Free Available (RoHS Compliant)
Applications
鈥?Motherboard Power Regulation for Computers
Ordering Information
PART NUMBER
ISL6524ACB*
ISL6524ACBZ* (Note)
ISL6524ACBZA-T (Note)
ISL6524EVAL1
TEMP.
RANGE
(掳C)
0 to 70
0 to 70
0 to 70
PACKAGE
28 Ld SOIC
PKG.
DWG.
#
M28.3
Pinout
ISL6524A (SOIC) TOP VIEW
DRIVE2 1
FIX 2
VID3 3
VID2 4
VID1 5
VID0 6
VID25 7
PGOOD 8
VTTPG 9
FAULT/RT 10
VSEN2 11
SS24 12
SS13 13
VSEN4 14
28 VCC
27 UGATE
26 PHASE
25 LGATE
24 PGND
23 OCSET
22 VSEN1
21 FB
20 COMP
19 VSEN3
18 DRIVE3
17 GND
16 VAUX
15 DRIVE4
28 Ld SOIC (Pb-free) M28.3
28 Ld SOIC (Pb-free) M28.3
Evaluation Board
*Add 鈥?T鈥?suffix for tape and reel.
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
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