MC10E111, MC100E111
5V ECL 1:9 Differential
Clock Driver
Description
The MC10E/100E111 is a low skew 1-to-9 differential driver,
designed with clock distribution in mind. It accepts one signal input,
which can be either differential or else single-ended if the V
BB
output
is used. The signal is fanned out to 9 identical differential outputs. An
enable input is also provided. A HIGH disables the device by forcing
all Q outputs LOW and all Q outputs HIGH.
The device is specifically designed, modeled and produced with low
skew as the key goal. Optimal design and layout serve to minimize
gate to gate skew within-device, and empirical modeling is used to
determine process control limits that ensure consistent t
pd
distributions from lot to lot. The net result is a dependable, guaranteed
low skew device.
The lowest TPD delay time results from terminating only one output
pair, and the greatest TPD delay time results from terminating all the
output pairs. This shift is about 10 鈥?20 pS in TPD. The skew between
any two output pairs within a device is typically about 25 nS. If other
output pairs are not terminated, the lowest TPD delay time results
from both output pairs and the skew is typically 25 nS. When all
outputs are terminated, the greatest TPD (delay time) occurs and all
outputs display about the same 10 鈥?20 pS increase in TPD, so the
relative skew between any two output pairs remains about 25 nS.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
The 100 Series contains temperature compensation.
Features
http://onsemi.com
PLCC鈭?8
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1
MCxxxE111G
AWLYYWW
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
*For additional marking information, refer to
Application Note AND8002/D.
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Guaranteed Skew Spec
Differential Design
V
BB
Output
PECL Mode Operating Range: V
CC
= 4.2 V to 5.7 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
=
鈭?.2
V to
鈭?.7
V
Internal Input 50 KW Pulldown Resistors
ESD Protection: Human Body Model; > 3 kV
Meets or Exceeds JEDEC Standard EIA/JESD78 IC
Latchup Test
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
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Moisture Sensitivity Level:
Pb = 1
Pb鈭扚ree = 3
For Additional Information, see Application Note
AND8003/D
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Flammability Rating: UL 94 V鈭? @ 0.125 in,
Oxygen Index: 28 to 34
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Transistor Count = 178 devices
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Pb鈭扚ree Packages are Available*
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
漏
Semiconductor Components Industries, LLC, 2006
November, 2006
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Rev. 16
1
Publication Order Number:
MC10E111/D
MC100E111FNG PDF文件相关型号
MC10E111_06
MC100E111FNG 产品属性
37
集成电路 (IC)
时钟/计时 - 时钟缓冲器，驱动器
100E
扇出缓冲器（分配）
1
1:9
是/是
ECL，PECL
ECL，PECL
800MHz
4.2 V ~ 5.7 V
-40°C ~ 85°C
表面贴装
28-LCC（J 形引线）
28-PLCC（11.51x11.51）
管件
MC100E111FNGOS
1
2
3
4
5
6
7
8
9
10
