MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
梅
2,
梅
4,
梅
8
Clock
MC10EL34
MC100EL34
Generation Chip
The MC10/100EL34 is a low skew
梅2, 梅4, 梅8
clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either
a differential or single-ended ECL or, if positive power supplies are used,
PECL input signal. In addition, by using the VBB output, a sinusoidal
source can be AC coupled into the device (see Interfacing section of the
ECLinPS鈩?Data Book DL140/D). If a single-ended input is to be used, the
VBB output should be connected to the CLK input and bypassed to ground
via a 0.01碌F capacitor. The VBB output is designed to act as the switching
reference for the input of the EL34 under single-ended input conditions,
as a result, this pin can only source/sink up to 0.5mA of current.
The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on
the internal clock when the device is enabled/disabled as can happen
with an asynchronous control. An internal runt pulse could lead to losing
synchronization between the internal divider stages. The internal enable
flip-flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of the
clock input.
Upon startup, the internal flip-flops will attain a random state; the
master reset (MR) input allows for the synchronization of the internal
dividers, as well as multiple EL34s in a system.
16
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B-05
PIN DESCRIPTION
PIN
CLK
EN
MR
VBB
Q0
Q1
Q2
FUNCTION
Diff Clock Inputs
Sync Enable
Master Reset
Reference Output
Diff
梅2
Outputs
Diff
梅4
Outputs
Diff
梅8
Outputs
FUNCTION TABLE
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
50ps Output-to-Output Skew
Synchronous Enable/Disable
Master Reset for Synchronization
75k鈩?Internal Input Pulldown Resistors
>1000V ESD Protection
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
CLK
VCC
16
EN
15
D
Q
梅2
Q
R
NC
14
CLK
13
CLK
12
VBB
11
MR
10
VEE
9
EN
L
H
X
MR
L
L
H
FUNCTION
Divide
Hold Q0鈥?
Reset Q0鈥?
Z
ZZ
X
R
梅4
Q
R
梅8
Q
R
Z = Low-to-High Transition
ZZ = High-to-Low Transition
1
Q0
2
Q0
3
VCC
4
Q1
5
Q1
6
VCC
7
Q2
8
Q2
12/93
漏
Motorola, Inc. 1996
3鈥?
REV 2
MC100EL34DR2 产品属性
2,500
集成电路 (IC)
时钟/计时 - 时钟发生器，PLL，频率合成器
100EL
时钟发生器
无
NECL，PECL
ECL
1
1:3
是/是
1.1GHz
是/无
±4.2 V ~ 5.7 V
-40°C ~ 85°C
表面贴装
16-SOIC（0.154"，3.90mm 宽）
16-SOIC
带卷 (TR)
1
2
3
