MC100EP016A
3.3 V ECL 8鈭払it
Synchronous Binary
Up Counter
Description
The MC100EP016A is a high鈭抯peed synchronous, presettable,
cascadeable 8鈭抌it binary counter. Architecture and operation are the
same as the ECLinPS鈩?family MC100E016 with higher operating
speed.
The counter features internal feedback to TC gated by the TCLD
(Terminal Count Load) pin. When TCLD is LOW (or left open, in
which case it is pulled LOW by the internal pulldowns), the TC
feedback is disabled, and counting proceeds continuously, with TC
going LOW to indicate an all鈭抩ne state. When TCLD is HIGH, the TC
feedback causes the counter to automatically reload upon TC = LOW,
thus functioning as a programmable counter. The Qn outputs do not
need to be terminated for the count function to operate properly. To
minimize noise and power, unused Q outputs should be left
unterminated.
COUT and COUT provide differential outputs from a single,
non鈭抍ascaded counter or divider application. COUT and COUT
should not be used in cascade configuration. Only TC should be used
for a counter or divider cascade chain output.
A differential clock input has also been added to improve
performance.
The 100 Series contains temperature compensation.
Features
http://onsemi.com
MARKING
DIAGRAM*
MC100
EP016A
AWLYYWWG
LQFP鈭?2
FA SUFFIX
CASE 873A
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
鈥?/div>
550 ps Typical Propagation Delay
鈥?/div>
Operation Frequency > 1.3 GHz is 30% Faster than MC100EP016
鈥?/div>
PECL Mode Operating Range: V
CC
= 3.0 V to 3.6 V
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
=
鈭?.0
V to
鈭?.6
V
Open Input Default State
Safety Clamp on Clock Inputs
Internal TC Feedback (Gated)
Addition of COUT and COUT
8鈭払it
Differential Clock Input
V
BB
Output
Fully Synchronous Counting and TC Generation
Asynchronous Master Reset
Pb鈭扚ree Packages are Available*
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
漏
Semiconductor Components Industries, LLC, 2006
November 2006
鈭?/div>
Rev. 6
1
Publication Order Number:
MC100EP016A/D
MC100EP016A_06 PDF文件相关型号
MC100EP016AFAG
MC100EP016A_06相关型号PDF文件下载
1
2
3
4
5
6
7
8
9
10
11
