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MC100LVEL30_06 Datasheet

  • MC100LVEL30_06

  • ON Semiconductor [3.3V ECL Triple D Flip−Flop wit...

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  • ONSEMI

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MC100LVEL30
3.3V ECL Triple D Flip鈭扚lop
with Set and Reset
Description
The MC100LVEL30 is a triple master鈭抯lave D flip鈭抐lop with
differential outputs. Data enters the master latch when the clock input
is LOW and transfers to the slave upon a positive transition on the
clock input.
In addition to a common Set input individual Reset inputs are
provided for each flip鈭抐lop. Both the Set and Reset inputs function
asynchronous and overriding with respect to the clock inputs.
Features
http://onsemi.com
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1200 MHz Minimum Toggle Frequency
450 ps Typical Propagation Delays
ESD Protection: >2 kV Human Body Model
The 100 Series Contains Temperature Compensation.
SO鈭?0 WB
DW SUFFIX
CASE 751D
PECL Mode Operating Range:
V
CC
= 3.0 V to 3.8 V with V
EE
= 0 V
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NECL Mode Operating Range:
V
CC
= 0 V with V
EE
=
鈭?.0
V to
鈭?.8
V
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Internal Input 75 kW Pulldown Resistors
MARKING DIAGRAM*
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Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
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Moisture Sensitivity:
20
100LVEL30
AWLYYWWG
Pb Pkg
Level 1,
Pb鈭扚ree Pkg
Level 3
For Additional Information, see Application Note AND8003/D
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Flammability Rating: UL 94 V鈭? @ 0.125 in,
Oxygen Index: 28 to 34
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Transistor Count = 347 devices
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
鈥?/div>
Pb鈭扚ree Packages are Available*
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
漏
Semiconductor Components Industries, LLC, 2006
November, 2006
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Rev. 7
1
Publication Order Number:
MC100LVEL30/D

MC100LVEL30_06 PDF文件相关型号

MC100LVEL30DWR2,MC100LVEL30DWR2G

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