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MC100LVEL56DWG Datasheet

  • MC100LVEL56DWG

  • ON Semiconductor [3.3V ECL Dual Differential 2:1 Multiplexe...

  • 120.25KB

  • ONSEMI

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MC100LVEL56
3.3V ECL Dual Differential
2:1 Multiplexer
Description
The MC100LVEL56 is a dual, fully differential 2:1 multiplexer. The
differential data path makes the device ideal for multiplexing low skew
clock or other skew sensitive signals.
The device features both individual and common select inputs to
address both data path and random logic applications.
The differential inputs have special circuitry which ensures device
stability under open input conditions. When both differential inputs are
left open the D input will pull down to V
EE
, The D input will bias
around V
CC
/2 forcing the Q output LOW.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and
V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking to
0.5 mA. When not used, V
BB
should be left open.
Features
http://onsemi.com
SO鈭?0 WB
DW SUFFIX
CASE 751D
MARKING DIAGRAM*
20
100LVEL56
AWLYYWWG
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
580 ps Typical Propagation Delays
Separate and Common Select
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range:
V
CC
= 3.0 V to 3.8 V with V
EE
= 0 V
NECL Mode Operating Range:
V
CC
= 0 V with V
EE
=
鈭?.0
V to
鈭?.8
V
Internal Input Pulldown Resistors on D(s), SEL(s), and COM_SEL
Q Output will Default LOW with Inputs Open or at V
EE
Pb鈭扚ree Packages are Available*
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
漏
Semiconductor Components Industries, LLC, 2006
November, 2006
鈭?/div>
Rev. 11
1
Publication Order Number:
MC100LVEL56/D

MC100LVEL56DWG PDF文件相关型号

MC100LVEL56DWR2

MC100LVEL56DWG 产品属性

  • 38

  • 集成电路 (IC)

  • 逻辑 - 信号开关，多路复用器，解码器

  • 100LVEL

  • 差分数字多路复用器

  • 2 x 2:1

  • 1

  • -

  • 双电源

  • 3 V ~ 3.8 V

  • -40°C ~ 85°C

  • 表面贴装

  • 20-SOIC（0.295"，7.50mm 宽）

  • 20-SOIC

  • 管件

  • MC100LVEL56DWGOS

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