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MC100LVELT22

3.3V Dual LVTTL/LVCMOS

to Differential LVPECL

Translator

Description

The MC100LVELT22 is a dual LVTTL/LVCMOS to differential

LVPECL translator. Because LVPECL (Low Voltage Positive ECL)

levels are used, only +3.3 V and ground are required. The small outline

8-lead package and the low skew, dual gate design of the LVELT22

makes it ideal for applications which require the translation of a clock

and a data signal.

Features

http://onsemi.com

MARKING

DIAGRAMS*

8

1

SOIC鈭?

D SUFFIX

CASE 751

8

1

TSSOP鈭?

DT SUFFIX

CASE 948R

8

KVT22

ALYW

G

1

鈥?/div>

350 ps Typical Propagation Delay

<100 ps Output鈭抰o鈭扥utput Skew

Flow Through Pinouts

The 100 Series Contains Temperature Compensation

LVPECL Operating Range: V

CC

= 3.0 V to 3.8 V

with GND = 0 V

鈥?/div>

When Unused TTL Input is left Open, Q Output will Default High

鈥?/div>

Pb鈭扚ree Packages are Available

8

KR22

ALYWG

G

1

DFN8

MN SUFFIX

CASE 506AA

A

L

Y

W

M

G

1

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Date Code

= Pb鈭扚ree Package

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

漏

Semiconductor Components Industries, LLC, 2007

1

March, 2007 鈭?Rev. 5

Publication Order Number:

MC100LVELT22/D

4I M

G

4

MC100LVELT22D,MC100LVELT22DG,MC100LVELT22DR2,MC100LVELT22DT

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