鈥?/div>
Pb鈭扚ree Packages are Available*
S1 5
D1 7
CE1 6
Q1
Q1
R1 4
C 9
R2 13
2
3
Table 1. TRUTH TABLE
D
L
H
X
X
X
C
L
L
L
H
H
CE
L
L
H
L
H
Q
n+1
L
H
Q
n
Q
n
Q
n
16
16
1
PDIP鈭?6
P SUFFIX
CASE 648
1
MC10H130P
AWLYYWWG
V
CC1
= PIN 1
V
CC2
= PIN 16
V
EE
= PIN 8
Q2
14
15
CE2 11
D2 10
S2 12
Q2
1 20
Figure 1. Logic Diagram
20 1
V
CC1
Q1
Q1
R1
S1
C
E1
D1
V
EE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC2
Q2
Q2
R2
S2
C
E2
D2
C
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
PLLC鈭?0
FN SUFFIX
CASE 775
10H130G
AWLYYWW
Pin assignment is for Dual鈭抜n鈭扡ine Package.
Figure 2. Pin Assignment
*For additional marking information, refer to
Application Note AND8002/D.
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
漏
Semiconductor Components Industries, LLC, 2006
February, 2006
鈭?/div>
Rev. 8
1
Publication Order Number:
MC10H130/D
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