鈥?/div>
Pb鈭扚ree Packages are Available*
Table 1. TRUTH TABLE
SELECT
OUTPUTS
OPERATING
S1
S2
Q0
n + 1
Q1
n + 1
Q2
n + 1
Q3
n + 1
MODE
L
L
H
H
L Parallel Entry
H
L
H
Shift Right*
Shift Left*
Stop Shift
D0
Q1
n
DL
Q0
n
D1
Q2
n
Q0
n
Q1
n
D2
Q3
n
Q1
n
Q2
n
D3
DR
Q2
n
32
n
16
16
1
PDIP鈭?6
P SUFFIX
CASE 648
1
MC10H141P
AWLYYWWG
* Outputs as exist after pulse appears at 鈥淐鈥?input with
input conditions as shown (Pulse Positive transition of
clock input).
1 20
V
CC1
Q2
Q3
C
DR
D3
S2
V
EE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC2
Q1
Q0
DL
D0
D1
S1
D2
20 1
PLLC鈭?0
FN SUFFIX
CASE 775
10H141G
AWLYYWW
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
Pin assignment is for Dual鈭抜n鈭扡ine Package.
Figure 1. Pin Assignment
*For additional marking information, refer to
Application Note AND8002/D.
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
漏
Semiconductor Components Industries, LLC, 2006
February, 2006
鈭?/div>
Rev. 8
1
Publication Order Number:
MC10H141/D
1
2
3
4
5
6
