鈥?/div>
MECL 10K鈥揅ompatible
LOGIC DIAGRAM
3
4
5
6
7
9
10
11
12
13
14
15
2
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
http://onsemi.com
MARKING
DIAGRAMS
16
CDIP鈥?6
L SUFFIX
CASE 620A
1
16
PDIP鈥?6
P SUFFIX
CASE 648
1
1
MC10H160P
AWLYYWW
MC10H160L
AWLYYWW
TRUTH TABLE
INPUT
Sum of
High Level
Inputs
Even
Odd
OUTPUT
Pin 2
Low
High
PLCC鈥?0
FN SUFFIX
CASE 775
10H160
AWLYYWW
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
DIP
PIN ASSIGNMENT
VCC1
OUT
IN1
IN2
IN3
IN4
IN5
VEE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC2
IN12
IN11
IN10
IN9
IN8
IN7
IN6
ORDERING INFORMATION
Device
MC10H160L
MC10H160P
MC10H160FN
Package
CDIP鈥?6
PDIP鈥?6
PLCC鈥?0
Shipping
25 Units/Rail
25 Units/Rail
46 Units/Rail
Pin assignment is for Dual鈥搃n鈥揕ine Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
漏
Semiconductor Components Industries, LLC, 2000
1
May, 2000 鈥?Rev. 7
Publication Order Number:
MC10H160/D