您的位置：维库电子市场网 > Datasheet > SI5325A-B-GM

SI5325A-B-GM Datasheet

  • SI5325A-B-GM

  • Silicon Laboratories [UP-PROGRAMMABLE PRECISION CLOCK MULTI...

  • 228.32KB

  • SILABS

阅览下载 纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

Si5325
P
R E L I M I N A R Y
D
A TA
S
H E E T
碌P-P
R O G R A M M A B L E
P
R E C I S I O N
C
L O C K
M
U L T I P L I E R
Description
The Si5325 is a low jitter, precision clock multiplier for
applications requiring clock multiplication without jitter
attenuation. The Si5325 accepts dual clock inputs ranging
from 10 to 710 MHz and generates two clock outputs ranging
from 10 to 945 MHz and select frequencies to 1.4 GHz. The
two outputs are divided down separately from a common
source. The device provides virtually any frequency
translation combination across this operating range. The
Si5325 input clock frequency and clock multiplication ratio
are programmable through an I
2
C or SPI interface. The
Si5325 is based on Silicon Laboratories' 3rd-generation
DSPLL
庐
technology, which provides any-rate frequency
synthesis in a highly integrated PLL solution that eliminates
the need for external VCXO and loop filter components. The
DSPLL loop bandwidth is digitally programmable, providing
jitter performance optimization at the application level.
Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5325
is ideal for providing clock multiplication in high performance
timing applications
.
Features
Generates any frequency from 10 to 945 MHz and
select frequencies to 1.4 GHz from an input
frequency of 10 to 710 MHz
Low jitter clock outputs w/jitter generation as low as
0.6 ps rms (30 kHz鈥?.3 MHz)
Integrated loop filter with selectable loop bandwidth
(150 kHz to 2 MHz)
Dual clock inputs w/manual or automatically
controlled hitless switching
Dual clock outputs with selectable signal format
(LVPECL, LVDS, CML, CMOS)
Support for ITU G.709 and custom FEC ratios
(255/238, 255/237, 255/236)
LOS, FOS alarm outputs
Digitally-controlled output phase adjust
I
2
C or SPI programmable
On-chip voltage regulator for 1.8, 2.5, or 3.3 V
卤10% operation
Small size: 6 x 6 mm 36-lead QFN
Pb-free, ROHS compliant
Applications
SONET/SDH OC-48/OC-192 line cards
GbE/10GbE, 1/2/4/8/10GFC line cards
ITU G.709 and custom FEC line cards
Optical modules
Wireless basestations
Data converter clocking
xDSL
SONET/SDH + PDH clock synthesis
Test and measurement
CKIN1
梅 N31
梅 NC1
CKOUT1
庐
CKIN2
梅 N32
DSPLL
梅 NC2
梅 N2
CKOUT2
Alarms
Signal Detect
Control
VDD (1.8, 2.5, or 3.3 V)
GND
I
2
C/SPI Port
Device Interrupt
Clock Select
Preliminary Rev. 0.26 7/07
Copyright 漏 2007 by Silicon Laboratories
Si5325
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

SI5325A-B-GM 产品属性

  • 50

  • 集成电路 (IC)

  • 时钟/计时 - 时钟发生器，PLL，频率合成器

  • DSPLL®

  • 时钟乘法器

  • 是

  • 时钟

  • CML，CMOS，LVDS，LVPECL

  • 1

  • 2:2

  • 是/是

  • 1.4GHz

  • 是/是

  • 1.62 V ~ 3.63 V

  • -40°C ~ 85°C

  • 表面贴装

  • 36-VFQFN 裸露焊盘

  • 36-QFN（6x6）

  • 管件

SI5325A-B-GM相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

©2025 维库电子市场网（www.dzsc.com）　备案号：浙B2-20050339-1 经营许可证：浙B2-20210386版权声明
买家服务热线：0571-85317607 | 买家服务部QQ： QQ:1609526468
卖家服务热线：0571-85317607 | 卖家服务部QQ： QQ:331652727

扫码下载APP，
一键连接广大的电子世界。

在线人工客服

买家服务：
卖家服务：
技术客服：

0571-85317607

网站技术支持

13606545031

客服在线时间周一至周五
9:00-17:30

关注官方微信号，
第一时间获取资讯。

建议反馈
返回顶部

建议反馈

联系人：

联系方式：

按住滑块，拖拽到最右边
>>
感谢您向阿库提出的宝贵意见，您的参与是维库提升服务的动力！意见一经采纳，将有感恩红包奉上哦！

PDF纠错X

投诉电话：0571-85317607 投诉QQ：

如选匿名将无法为您反馈投诉结果，建议实名投诉！