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TMSC6701数据手册封面

TMSC6701 Datasheet

  • TMSC6701

  • FLOATING POINT DIGITAL SIGNAL PROCESSOR

  • 862.88KB

  • TI

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TMS320C6701
FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E 鈥?MAY 1998 鈥?REVISED MAY 2000
D
Highest Performance Floating-Point Digital
Signal Processor (DSP) TMS320C6701
鈥?8.3-, 6.7-, 6-ns Instruction Cycle Time
鈥?120-, 150-, 167-MHz Clock Rate
鈥?Eight 32-Bit Instructions/Cycle
鈥?1 GFLOPS
鈥?TMS320C6201 Fixed-Point DSP
Pin-Compatible
VelociTI鈩?Advanced Very Long Instruction
Word (VLIW) 鈥機67x CPU Core
鈥?Eight Highly Independent Functional
Units:
鈥?Four ALUs (Floating- and Fixed-Point)
鈥?Two ALUs (Fixed-Point)
鈥?Two Multipliers (Floating- and
Fixed-Point)
鈥?Load-Store Architecture With 32 32-Bit
General-Purpose Registers
鈥?Instruction Packing Reduces Code Size
鈥?All Instructions Conditional
Instruction Set Features
鈥?Hardware Support for IEEE
Single-Precision Instructions
鈥?Hardware Support for IEEE
Double-Precision Instructions
鈥?Byte-Addressable (8-, 16-, 32-Bit Data)
鈥?8-Bit Overflow Protection
鈥?Saturation
鈥?Bit-Field Extract, Set, Clear
鈥?Bit-Counting
鈥?Normalization
1M-Bit On-Chip SRAM
鈥?512K-Bit Internal Program/Cache
(16K 32-Bit Instructions)
鈥?512K-Bit Dual-Access Internal Data
(64K Bytes)
32-Bit External Memory Interface (EMIF)
鈥?Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
鈥?Glueless Interface to Asynchronous
Memories: SRAM and EPROM
鈥?52M-Byte Addressable External Memory
Space
Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
With an Auxiliary Channel
26
GJC (352-PIN BGA) PACKAGE
(BOTTOM VIEW)
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J
K
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16-Bit Host-Port Interface (HPI)
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鈥?Access to Entire Memory Map
Two Multichannel Buffered Serial Ports
(McBSPs)
鈥?Direct Interface to T1/E1, MVIP, SCSA
Framers
鈥?ST-Bus-Switching Compatible
鈥?Up to 256 Channels Each
鈥?AC97-Compatible
鈥?Serial-Peripheral-Interface (SPI)
Compatible (Motorola鈩?
Two 32-Bit General-Purpose Timers
Flexible Phase-Locked-Loop (PLL) Clock
Generator
IEEE-1149.1 (JTAG
鈥?/div>
)
Boundary-Scan-Compatible
352-Pin Ball Grid Array (BGA) Package
(GJC Suffix)
0.18-碌m/5-Level Metal Process
鈥?CMOS Technology
3.3-V I/Os, 1.8-V Internal (120-, 150-MHz)
3.3-V I/Os, 1.9-V Internal (167-MHz Only)
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VelociTI is a trademark of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
鈥?IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
2000, Texas Instruments Incorporated
POST OFFICE BOX 1443
鈥?/div>
HOUSTON, TEXAS 77251鈥?443
1

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