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Quartus 5.0中Verilog HDL的预编译命令的使用

作者：jaky202　栏目：EDA技术

Quartus 5.0中Verilog HDL的预编译命令的使用
我在使用Verilog HDL语言编写程序后，用Quartus 5.0软件编译的时候显示如下的错误信息：

Error: Verilog HDL syntax error at zhb.v(118) near text ".";  expecting an identifier, or a NUMBER, or a SYSTEM task, or "(", or "{", or unary operator,
Error: Verilog HDL syntax error at zhb.v(118) near text ",";  expecting ";"
Error: Verilog HDL syntax error at zhb.v(119) near text "myadder0";  expecting "<=", or "="
Error: Verilog HDL syntax error at zhb.v(120) near text "mymul1";  expecting "<=", or "="
Error: Verilog HDL syntax error at zhb.v(122) near text "myadder1";  expecting "<=", or "="
Error: Verilog HDL Task Definition error at zhb.v(118): task "T1" is not used as a task
Error: Ignored MODULE "zhb" at zhb.v(69) because of previous errors

我的程序如下：
MODULE counter1(clk,d1,d2,T1,T0);
input  clk, d1,d2;
OUTPUT  [31:0] T1,T0;
reg     [31:0]  T1,T0;
always  @ (posedge clk)

        begin
            if(d1)
                begin
                    T1<=T1+1;
                    if(!d2)
                    T0<=T0+1;
                    else T0<=0;
                end
            else  T1<=0;
        end
endMODULE

MODULE counter2(clk,d2,T2);
input  clk,d2;
OUTPUT  [19:0] T2;
reg     [19:0] T2;
always @(posedge clk)     //时钟上升沿触发
            begin
                if(d2)   //使能端信号，高电平时，开始加法计数
                    T2<=T2+1;
                    else   T2<=0;  //使能端为高时，计数器不动作，输出端保持为零//
            end
endMODULE
//加法器
MODULE  adder(x,y,sum,);
input  [27:0]  x,y;
OUTPUT  [27:0]  sum;
wire    [27:0]   x,y;
reg     [27:0]  sum;

always    @(x or y)
    begin
        sum=x+y;
    end
endMODULE
//除法器
MODULE  divide(
                    x,
                    y,
                    quo      //quotient  商
                    );
input  [27:0]  x,y;
OUTPUT  [27:0]   quo;
wire  [27:0]  x,y;
reg   [0:27]  quo;
always  @(x or y)
        quo=x/y;
endMODULE
//乘法器
MODULE  mul(x,y,z);
input  [27:0]  x,y;
OUTPUT  [27:0]   z;
wire  [27:0] x,y;
reg   [27:0]  z;
always  @ (x or y )
    z=x*y;
endMODULE
'include "counter1.v"
'include "counter2.v"
'include "adder.v"
'include "divide.v"
'include "mul.v"
MODULE zhb (
                clk,
                d1,
                d2,
                T0,
                T1,
                T2,
                s1,
                s2,
                T,
                V,
                k
                );
input clk;
input d1;
input d2;
input s1;
input s2;
OUTPUT [19:0] T0;
OUTPUT [19:0] T1;
OUTPUT [19:0] T2;
OUTPUT [19:0] T;
OUTPUT [27:0] V;
OUTPUT k;

wire clk;
wire d1;
wire d2;
wire s1;
wire s2;
reg  [19:0] T0;
reg  [19:0] T1;
reg  [19:0] T2;
reg  [19:0] T;
reg  [27:0] V;
reg k;
//中间变量
reg temp0;
reg temp1;
reg temp2;
reg temp3;
reg temp4;
reg temp5;
reg temp6;

counter1 mycounter1(.clk(clk),.d1(d1),.d2(d2),.T1(T1),.T0(T0));
counter2 mycounter2(.clk(clk),.d2(d2),.T2(T2));
always @(posedge d1)
    begin
        mul mymul0 (.s1(x),.T1(y),.temp0(z));
        adder myadder0(.s1(x),.s2(y),.temp1(sum));
        mul mymul1 (.T0(x),.temp1(y),.temp3(z));
        temp4=2*temp3;
        adder myadder1 (.temp0(x),.temp4(y),.temp5(sum));
        temp6=2*s1;
        T=temp5/temp6;
        V=s1/T0;
        #T k=1;
        #1 k=0;

    end
endMODULE
那位高手指点下呀，改怎么修改呢？！

2楼：

>>参与讨论

作者： cpld163 于 2006/5/27 21:27:00 发布：

....
quo=x/y;//应该要加上begin吧
  z=x*y;//应该要加上begin吧
  reg TEMP0;//应该是wire类型吧

always @(posedge d1)//这样写，不能够被综合把
    begin
        mul mymul0 (.s1(x),.T1(y),.TEMP0(z));//x是28位的，s1是一位！！！
        adder myadder0(.s1(x),.s2(y),.TEMP1(sum));//sum是28位，TEMP是一位!!!
        mul mymul1 (.T0(x),.TEMP1(y),.TEMP3(z));//同上
        TEMP4=2*TEMP3;
        adder myadder1 (.TEMP0(x),.TEMP4(y),.TEMP5(sum));//同上
        TEMP6=2*s1;
        T=TEMP5/TEMP6;
        V=s1/T0;
        #T k=1; // #T这样的延时不能够被综合,这些写等于是先k=1,然后立即等于0.
        #1 k=0;

    end
endmodule

最后那个always不知道什么意思，绝对不能综合。不知道为什么这样写？？

参与讨论

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