特性

Fixed Feedback Path for Lowest InputtoOutput Delay

Eight Dedicated OE# Pins for Hardware Control of Outputs

PLL Bypass Configurable for PLL or Fanout Operation

Selectable PLL Bandwidth

Spread Spectrum Compatible: Tracks Input Clock Spreading for Low EMI

SMBus Programmable Configurations

100 MHz and 133 MHz PLL Mode to Meet the Next Generation PCIe Gen2 / Gen 3 and Intel QPI Phase Jitter

2 TriLevel Addresses Selection (Nine SMBUS Addresses)

CycletoCycle Jitter: < 50 ps

OutputtoOutput Skew: < 65 ps

InputtoOutput Delay: Fixed at 0 ps

InputtoOutput Delay Variation: < 50 ps

Phase Jitter: PCIe Gen3 < 1 ps rms

Phase Jitter: QPI 9.6GB/s < 0.2 ps rms

QFN 72pin Package, 10 mm x 10 mm

These are PbFree Devices

描述

    The NB3N1900K differential clock buffers are designed to work in conjunction with a PCIe compliant source clock synthesizer to provide pointtopoint clocks to multiple agents. The device is capable of distributing the reference clocks for Intel QuickPath Interconnect (Intel QPI), PCIe Gen1, Gen2, Gen3. The NB3N1900K internal PLL is optimized to support 100 MHz and 133 MHz frequency operation. The NB3N1900K supports HCSL output levels.

应用

    Industrial

    Networking

    Computing

    Consumer

    Desktop

    Notebook

    Switchers/Routers

    Servers

    Set Top Box

    Automated Test Equipment