特性

High Performance LVPECL and LVCMOS PLL Clock Synchronizer

Two Reference Clock Inputs (Primary and Secondary Clock) for

Redundancy Support With Manual or Automatic Selection

Accepts LVCMOS Input Frequencies Up to 200 MHz

VCXO_IN Clock is Synchronized to One of the Two Reference Clocks

VCXO_IN Frequencies Up to 2 GHz (LVPECL)

Outputs Can Be a Combination of LVPECL and LVCMOS (Up to Five

Differential LVPECL Outputs or Up to 10 LVCMOS Outputs)

Output Frequency is Selectable by x1, /2, /3, /4, /6, /8, /16 on

Each Output Individually

Efficient Jitter Cleaning From Low PLL Loop Bandwidth

Low Phase Noise PLL Core

Programmable Phase Offset (PRI_REF and SEC_REF to Outputs)

Wide Charge Pump Current Range From 200 μA to 3 mA

Dedicated Charge Pump Supply (VCC_CP) for Wide Tuning Voltage

Range VCOs

Presets Charge Pump to VCC_CP/2 for Fast Center Frequency

Setting of VC(X)O

Analog and Digital PLL Lock Indication

Provides VBB Bias Voltage Output for Single-Ended Input Signals

(VCXO_IN)

Frequency Hold Over Mode Improves Fail-Safe Operation

Power-Up Control Forces LVPECL Outputs to 3-State at VCC

< 1.5 V

SPI Controllable Device Setting

3.3-V Power Supply

High-Performance 52 Pin Ceramic Quad Flat Pack (HFG)

Rad-Tolerant : 50kRad (Si) TID

QML-V Qualified, SMD 5962-07230

Military Temperature Range

(–55°C to 125°C Tcase)

Engineering Evaluation (/EM) Samples are Available(1)

(1) These units are intended for engineering evaluation only. They are processed to a non-compliant flow (e.g. no burn-in, etc.) and are tested to temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance on full MIL specified temperature range of –55°C to 125°C or operating life.

描述

The CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O:

VC(X)O_IN / PRI_REF = (N x P) / M or

VC(X)O_IN / SEC_REF = (N x P) / M

VC(X)O_IN clock operates up to 2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements.

The CDCM7005 can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005 are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The LVCMOS outputs are arranged in pairs (Y0A:Y0B, Y1A:Y1B, …), so that each pair has the same frequency. But each output can be separately inverted and disabled. The built in synchronization latches ensure that all outputs are synchronized for low output skew.

All device settings, like outputs signaling, divider value, input selection, and many more, are programmable by SPI (3-wire serial peripheral interface). SPI allows individually control of the device settings.

The device operates in a 3.3-V environment and is characterized for operation from –55°C to 125°C (Tcase).

应用

军用：雷达/电子战

卫星有效载荷：太阳传感器

太空：卫星有效载荷

卫星有效载荷：合成孔径雷达 (SAR)

卫星有效载荷：陀螺仪传感器