鈥?/div>
A, B, C and D speed grades
Low input and output leakage
鈮?碌A
(max.)
CMOS power levels
True TTL input and output compatibility
鈥?V
OH
= 3.3V (typ.)
鈥?V
OL
= 0.3V (typ.)
High drive outputs (-15mA I
OH
, 48mA I
OL
)
Meets or exceeds JEDEC standard 18 specifications
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
Available in DIP, SOIC, SSOP, QSOP, CERPACK and
LCC packages
DESCRIPTION:
The IDT29FCT520AT/BT/CT/DT and IDT29FCT521AT/
BT/CT/DT each contain four 8-bit positive edge-triggered
registers. These may be operated as a dual 2-level or as a
single 4-level pipeline. A single 8-bit input is provided and any
of the four registers is available at the 8-bit, 3-state output.
These devices differ only in the way data is loaded into and
between the registers in 2-level operation. The difference is
illustrated in Figure 1. In the IDT29FCT520AT/BT/CT/DT
when data is entered into the first level (I = 2 or I = 1), the
existing data in the first level is moved to the second level. In
the IDT29FCT521AT/BT/CT/DT, these instructions simply
cause the data in the first level to be overwritten. Transfer of
data to the second level is achieved using the 4-level shift
instruction (I = 0). This transfer also causes the first level to
change. In either part I=3 is for hold.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
FUNCTIONAL BLOCK DIAGRAM
D
0
-D
7
8
MUX
I
0
,I
1
2
REGISTER
CONTROL
CLK
1
OCTAL REG. A1
OCTAL REG. B1
OCTAL REG. A2
OCTAL REG. B2
S
0
,S
1
2
MUX
OE
8
2619 drw 01
Y
0
-Y
7
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
漏1994
Integrated Device Technology, Inc.
APRIL 1994
DSC-4215/4
6.2
1
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