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74VHCT126A数据手册封面

74VHCT126A Datasheet

  • 74VHCT126A

  • QUAD BUS BUFFER (3-STATE)

  • 149.34KB

  • STMicroelectronics

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庐
74VHCT126A
QUAD BUS BUFFERS (3-STATE)
PRELIMINARY DATA
s
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 5 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
碌A
(MAX.) at T
A
= 25
o
C
COMPATIBLE WITH TTL OUTPUTS:
V
IH
= 2V (MIN), V
IL
= 0.8V (MAX)
POWER DOWN PROTECTION ON INPUTS &
OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 126
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
OLP
= 0.8V (Max.)
SOP
PACKAGE
SOP
TSSOP
T UBE
74VHCT126AM
TSSOP
T& R
74VHCT126AMTR
74VHCT126ATTR
ORDER CODES
DESCRIPTION
The 74VHCT126A is an advanced high-speed
CMOS QUAD BUS BUFFERS fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
This device requires the 3-STATE control input G
to be set low to place the output into the high
impedance state.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
March 2000
1/8

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