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CY62148V Datasheet

  • CY62148V

  • 512K x 8 MoBL Static RAM

  • 195.41KB

  • Cypress

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MoBL
CY62148V MoBL鈩?/div>
512K x 8 MoBL Static RAM
Features
鈥?Low voltage range:
鈥?2.7V鈥?.6V
鈥?Ultra low active power
鈥?Low standby power
鈥?TTL-compatible inputs and outputs
鈥?Automatic power-down when deselected
鈥?CMOS for optimum speed/power
The device can be put into standby mode when deselected
(CE HIGH).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
0
through I/O
7
) is then written into the location speci-
fied on the address pins (A
0
through A
18
).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW and WE LOW).
The CY62148V is available in a 36-ball FBGA, 32 pin TSOPII,
and a 32-pin SOIC package.
Functional Description
The CY62148V is a high-performance CMOS static RAM or-
ganized as 524,288 words by 8 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life鈩?(MoBL鈩? in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption by 99% when addresses are not toggling.
Logic Block Diagram
Data in Drivers
I/O
0
I/O
1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
ROW DECODER
SENSE AMPS
I/O
2
I/O
3
I/O
4
I/O
5
512K x 8
ARRAY
CE
WE
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
OE
62148V-1
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134
鈥?/div>
408-943-2600
March 23, 2000

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