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GS8322Z36E-225T Datasheet

  • GS8322Z36E-225T

  • 36Mb Pipelined and Flow Through Synchronous NBT SRAM

  • 758.01KB

  • 39页

  • ETC

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GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)
119, 165 & 209 BGA
Commercial Temp
Industrial Temp
Features
鈥?NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM鈩? NoBL鈩?and
ZBT鈩?SRAMs
鈥?2.5 V or 3.3 V +10%/鈥?0% core power supply
鈥?2.5 V or 3.3 V I/O supply
鈥?User-configurable Pipeline and Flow Through mode
鈥?ZQ mode pin for user-selectable high/low output drive
鈥?IEEE 1149.1 JTAG-compatible Boundary Scan
鈥?LBO pin for Linear or Interleave Burst mode
鈥?Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices
鈥?Byte write operation (9-bit Bytes)
鈥?3 chip enable signals for easy depth expansion
鈥?ZZ Pin for automatic power-down
鈥?JEDEC-standard 119-, 165- or 209-Bump BGA package
36Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz鈥?33 MHz 2.5
V or 3.3 V V
DD
2.5 V or 3.3 V I/O
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8322Z18/36/72 may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8322Z18/36/72 is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 119-bump, 165-bump or 209-bump BGA package.
Functional Description
The GS8322Z18/36/72 is a 36Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Parameter Synopsis
t
KQ(x18/x36)
t
KQ(x72)
tCycle
Curr
(x18)
Curr
(x36)
Curr
(x72)
t
KQ
tCycle
Curr
(x18)
Curr
(x36)
Curr
(x72)
-250 -225 -200
2.5 2.7 3.0
3.0 3.0 3.0
4.0 4.4 5.0
285
350
440
6.5
6.5
205
235
315
-166
3.5
3.5
6.0
-150
3.8
3.8
6.7
-133 Unit
4.0 ns
4.0 ns
7.5 ns
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
265 245 220 210 185 mA
320 295 260 240 215 mA
410 370 320 300 265 mA
7.0 7.5 8.0 8.5 8.5 ns
7.0 7.5 8.0 8.5 8.5 ns
195 185 175 165 155 mA
225 210 200 190 175 mA
295 265 255 240 230 mA
Rev: 11/1/04
1/38
漏 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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