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HCF4099数据手册封面

HCF4099 Datasheet

  • HCF4099

  • 8-BIT ADDRESSABLE LATCH

  • 590.52KB

  • STMicroelectronics   STMicroelectronics

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HCC/HCF4099B
8-BIT ADDRESSABLE LATCH
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SERIAL DATA INPUT - ACTIVE PARALLEL
OUTPUT
STORAGE REGISTER CAPABILITY - MASTER
CLEAR
CAN FUNCTION AS DEMULTIPLEXER
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
QUIESCENT CURRENT SPECIFIED TO 20V
FOR HCC DEVICE
5V, 10V, AND 15V PARAMETRIC RATINGS
INPUT CURRENT OF 100nA AT 18V AND 25掳C
FOR HCC DEVICE
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC TEN-
TATIVE STANDARD N掳. 13A, 鈥漇TANDARD
SPECIFICATIONS FOR DESCRIPTION OF 鈥滲鈥?/div>
SERIES CMOS DEVICES鈥?/div>
EY
Plastic Package
F
Ceramic Frit Seal Package
M1
Micro Package
C1
Plastic Chip Carrier
ORDER CODES
:
HCC4099BF
HCF4099BM1
HCF4099BEY
HCF4099BC1
PIN CONNECTIONS
DESCRIPTION
The
HCC4099B
(extended temperature range) and
HCF4099B
(intermediate temperature range) are
monolithic integrated circuits, available in 16-lead dual
in-line plastic or ceramic package and plastic micro
package. The HCC/HCF4099B 8-bit addressable
latch is a serial-input, parallel-output storage register
that can perform a variety of functions. Data are in-
putted to a particular bit in the latch when that bit is
addressed (by means of inputs A0, A1, A2) and
when WRITE DISABLE is at a low level. When
WRITE DISABLE is high, data entry is inhibited ;
however, all 8 outputs can be continuously read in-
dependent of WRITE DISABLE and address inputs.
A master RESET input is available, which resets all
bits to a logic 鈥?鈥?level when RESET and WRITE
DISABLE are at a high level. When RESET is at a
high level, and WRITE DISABLE is at a low level, the
latch acts as a 1-of-8 demultiplexer ; the bit that is
addressed has an active output which follows the
data input, while all unaddressed bits are held to a
logic 鈥?鈥?level.
September 1988
1/14

HCF4099 PDF文件相关型号

HCF4099BEY,HCF4099BM1,HCF4099M013TR

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