based, low-skew zero delay buffer. Based on ICS鈥?/div>
proprietary low jitter Phase Locked Loop (PLL)
techniques, the device provides eight low skew outputs
at speeds up to 133 MHz at 3.3 V. The outputs can be
generated from the PLL (for zero delay), or directly
from the input (for testing), and can be set to tri-state
mode or to stop at a low level. The PLL feedback is
on-chip and is obtained from the CLKOUT pad.
The ICS2309 is available in two different versions. The
ICS2309-1 is the base part. The ICS2309-1H is a high
drive version with faster rise and fall times.
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Clock outputs from 10 to 133 MHz
Zero input-output delay
Eight low skew (<250 ps) outputs
Device-to-device skew <700 ps
Full CMOS outputs with 25 mA output drive
capability at TTL levels
5 V tolerant CLKIN
Tri-state mode for board-level testing
Advanced, low power, sub-micron CMOS process
Operating voltage of 3.3 V
Industrial temperature range available
Packaged in 16-pin SOIC and TSSOP (-1H version
only)
(16-pin TSSOP only)
鈥?/div>
Pb (lead) free package available for -1H version
Block Diagram
VDD
2
CLKIN
PLL
0
CLKOUT
1
CLKA1
CLKA2
CLKA3
CLKA4
S2, S1 2
Control
Logic
CLKB1
CLKB2
CLKB3
CLKB4
GND
2
MDS 2309 D
I n t e gra te d C i r c u i t S y s te m s
鈼?/div>
1
52 5 Ra ce Street, San Jose, CA 9 512 6
鈼?/div>
Revision 052405
tel (408 ) 297 -120 1
鈼?/div>
w ww.i c s t. c om
ICS2309M-1HT 产品属性
2,500
集成电路 (IC)
时钟/计时 - 时钟发生器，PLL，频率合成器
-
扇出缓冲器（分配），零延迟缓冲
带旁路
时钟
CMOS，TTL
1
1:9
无/无
133MHz
无/无
3 V ~ 3.6 V
0°C ~ 70°C
表面贴装
16-SOIC（0.154"，3.90mm 宽）
16-SOIC
带卷 (TR)
2309M-1HT
ICS2309M-1HT相关型号PDF文件下载
-
型号
版本
描述
厂商
下载
-
英文版
SMPTE Time Code Receiver/Generator
ICS
-
英文版
SMPTE Time Code Receiver/Generator
ICST [Inte...
-
英文版
FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
IDT [Integ...
-
英文版
Field Programmable Dual Output SS VersaClock Synthesizer
ICST [Inte...
-
英文版
Triple PLL Field Programmable VCXO Clock Synthesizer
ICS
-
英文版
Triple PLL Field Programmable VCXO Clock Synthesizer
ICST [Inte...
-
英文版
Triple PLL Field Programmable VCXO Clock Synthesizer
ICST [Inte...
-
英文版
Triple PLL Field Programmable VCXO Clock Synthesizer
ICST [Inte...
-
英文版
Triple PLL Field Programmable VCXO Clock Synthesizer
ICST [Inte...
-
英文版
Package Outline and Package Dimensions (16-pin TSSOP,173 Mil...
ICSI
-
英文版
Package Outline and Package Dimensions (16-pin TSSOP,173 Mil...
ICSI [Inte...
-
英文版
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
ICST [Inte...
-
英文版
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
ICST [Inte...
-
英文版
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
ICST [Inte...
-
英文版
Wavedec Digital Audio Codec
ICS
-
英文版
Wavedec Digital Audio Codec
ICST [Inte...
-
英文版
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
ICS
-
英文版
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
ICST [Inte...
-
英文版
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
ICS
-
英文版
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
ICST [Inte...
1
2
3
4
5
6
7
8
9
