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Packaged as 8-pin SOIC or die
Available in Pb (lead) free package
ICS鈥?lowest cost PLL clock
Zero ppm multiplication error
Input crystal frequency of 5 - 27 MHz
Input clock frequency of 2 - 50 MHz
Output clock frequencies up to 160 MHz
Extremely low jitter of 25 ps (one sigma)
Compatible with all popular CPUs
Duty cycle of 45/55 up to 160 MHz
Nine selectable frequencies
Operating voltage of 3.3V or 5.5V
Tri-state output for board level testing
25mA drive capability at TTL levels
Ideal for oscillator replacement
Industrial temperature version available
Advanced, low-power CMOS process
Block Diagram
VDD
S1:0
X1/ICLK
Crystal or
Clock input
X2
2
Crystal
Oscillator
PLL Clock
Multiplier
Circuitry
and ROM
CLK
Optional crystal capacitors
GND
OE
MDS 501 K
I n t e gra te d C i r c u i t S y s t e m s
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1
5 25 Race Stre et, San Jo se, CA 9 5126
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Revision 071304
te l (40 8) 2 97-12 01
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