PRELIMINARY INFORMATION
ICS503
LOCO鈩?PLL Clock Multiplier
Features
鈥?Packaged as 8 pin SOIC or die
鈥?ICS鈥?lowest cost PLL clock family
鈥?Generates 16.9344 MHz for stereo codecs from
the 14.31818 MHz motherboard clock
鈥?Can be cost effective in replacing a single
surface-mount crystal
鈥?Can be driven by other 5xx series
鈥?Input crystal frequency of 5 - 27 MHz
鈥?Input clock frequency of 2 - 50 MHz
鈥?Output clock frequencies up to 160 MHz
鈥?Low jitter - 50 ps one sigma
鈥?Duty cycle of 45/55 up to 160 MHz
鈥?Operating voltages of 3.0 to 5.5V
鈥?Full CMOS level outputs with 25mA drive
capability at TTL levels
鈥?Advanced, low power CMOS process
Description
The ICS503 is a member of the LOCO鈩?family,
the most cost effective way to generate a high
quality, high frequency clock output from a low
frequency crystal or clock input. The name LOCO
stands for LOw Cost Oscillator, as it is designed
to replace crystals and crystal oscillators in most
electronic systems. Using Phase-Locked-Loop
(PLL) techniques, the device uses a standard
fundamental mode, inexpensive crystal to produce
output clocks up to 160 MHz.
Stored in the chip鈥檚 ROM is the ability to generate
9 different multiplication factors, allowing one
chip to be used in two or three different
applications (see page 2).
Block Diagram
VDD GND
S0
S1
Crystal or
clock input
X1/ICLK
Crystal
Oscillator
X2
PLL
Clock Multiplier
Circuitry
and
ROM
Output
Buffer
CLK
Optional crystal capacitors
MDS 503 A
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Revision 111000
Integrated Circuit Systems, Inc. 鈥?525 Race Street 鈥?San Jose 鈥A鈥?5126鈥?408) 295-9800tel 鈥?www.icst.com
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