analog/digital Phase Locked Loop (PLL) techniques.
in 1992 with the debut of the AV9170. The
鈩?/div>
family, was
designed as a performance upgrade to meet today鈥檚
higher speed and lower voltage requirements. The
zero delay feature means that the rising edge of the
input clock aligns with the rising edges of both
outputs, giving the appearance of no delay through
the device. There are two outputs on the chip, one
being a low-skew divide by two of the other. The chip
has an all-chip power down/tri-state mode that stops
the internal PLL and puts both outputs into the high
impedance state.
The chip is ideal for synchronizing outputs in a large
variety of systems, from personal computers to data
communications to video. By allowing off-chip
feedback paths, the ICS570A can eliminate the delay
through other devices.
The ICS570A was done to improve jitter from the
original ICS570, and so it is recommended for all new
designs.
Features
鈥?Packaged in 8 pin SOIC.
鈥?Pin-for-pin replacement and upgrade to ICS570
鈥?Functional equivalent to AV9170 (not a pin-
for-pin replacement).
鈥?Low input to output skew of 500 ps max.
鈥?Low skew (250 ps) outputs. One is 梅 2 of other.
鈥?Ability to choose between 14 different
multipliers from 0.5X to 32X.
鈥?Input clock frequency up to 150 MHz at 3.3V.
鈥?Can recover poor input clock duty cycle.
鈥?Output clock duty cycle of 45/55.
鈥?Power Down and Tri-State Mode.
鈥?Full CMOS clock swings with 25mA drive
capability at TTL levels.
鈥?Advanced, low power CMOS process.
鈥?Operating voltage of 3.0 to 5.5 V.
鈥?Industrial temperature version available
Block Diagram
ICLK
S1, S0
2
FBIN
divide by
N
Phase
Detector,
Charge
Pump, and
Loop Filter
Voltage
Controlled
Oscillator
梅2
Output
Buffer
CLK
Output
Buffer
CLK/2
External feedback can come from CLK or CLK/2 (see table on page 2).
1
Revision 102700
Printed 11/14/00
Integrated Circuit Systems, Inc .鈥?525 Race Street 鈥?San Jose 鈥?CA 鈥?5126鈥?(408)295-9800tel 鈥ww.icst.com
MDS 570A C
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