ICS574
Zero Delay, Low Skew Buffer
Description
The ICS574 is a low jitter, low-skew, high performance
PLL-based zero delay buffer for high speed
applications. Based on ICS鈥檚 proprietary low jitter
Phase Locked Loop (PLL) techniques, the device
provides four low skew outputs at speeds up to 160
MHz at 3.3 V. When one of the outputs is connected
directly to FBIN, the rising edge of each output is
aligned with the rising edge of the input clock. External
delay elements connected in the feedback loops will
cause the outputs to occur before the inputs by the
amount of propagation delay of the external element.
ICS manufactures the largest variety of clock
generators and buffers, and is the largest clock
supplier in the world.
Features
鈥?Packaged in 8 pin narrow SOIC
鈥?Zero input-to-output delay
鈥?Four 1X outputs
鈥?Output to output skew is less than 150 ps
鈥?Output clocks up to 160 MHz at 3.3 V
鈥?External feedback path for output edge placement
鈥?Spread Smart鈩?technology works with spread
spectrum clock generators
鈥?Full CMOS outputs with 18 mA output drive
capability at TTL levels at 3.3 V
鈥?Advanced, low power, sub-micron CMOS process
鈥?Operating voltage from 3.0 to 5.5 V
Block Diagram
CLK1
FBIN
CLKIN
PLL
CLK2
CLK3
CLK4
MDS 574 B
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Revision 051801
Integrated Circuit Systems, Inc. 鈥?525 Race Street 鈥?San Jose 鈥?CA 鈥?95126 鈥?(408)295-9800 鈥?www.icst.com
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