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ICS673M-01T Datasheet

  • ICS673M-01T

  • PLL Building Block

  • 77.61KB

  • 9页

  • ICS

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ICS673-01
PLL Building Block
Description
The ICS673-01 is a low cost, high performance
Phase Locked Loop (PLL) designed for clock
synthesis and synchronization. Included on the
chip are the phase detector, charge pump, Voltage
Controlled Oscillator (VCO), and two output
buffers. One output buffer is a divide by two of
the other. Through the use of external reference
and VCO dividers (easily implemented with the
ICS674-01), the user can easily customize the
clock to lock to a wide variety of input frequencies.
Included on the ICS673-01 are an Output Enable
function that puts both outputs into a high-
impedance state, as well as a Power Down feature
that turns off the entire device.
Features
鈥?Packaged in 16 pin narrow SOIC
鈥?Access to VCO input and feedback paths of PLL
鈥?VCO operating range up to 135 MHz (5V)
鈥?Able to lock MHz range outputs to kHz range
inputs through use of external dividers
鈥?Output Enable tri-states outputs
鈥?Low skew output clocks
鈥?Power Down turns off chip
鈥?VCO predivide of 1 or 4
鈥?25 mA output drive capability at TTL levels
鈥?Advanced, low power, sub-micron CMOS process
鈥?+3.3 V 卤5% or +5 V 卤10% operating voltage
鈥?Industrial Temperature range available
鈥?With the ICS674-01, forms a complete PLL
Block Diagram
VDD GND
2
3
CHGP
VDD
VCOIN
REFIN
UP
Ic
FBIN
Phase/
Frequency
DOWN
Detector
Ic
VCO
梅4
1
MUX
0
梅2
Output
Buffer
CLK1
PD
(entire chip)
Output
Buffer
CLK2
CAP
SEL
OE (both outputs)
1
Revision 022500
Printed 11/15/00
Integrated Circuit Systems, Inc. 鈥?525 Race Street 鈥?San Jose 鈥?CA 鈥?95126鈥?408)295-9800tel 鈥?www.icst.com
MDS 673-01 D

ICS673M-01T 产品属性

  • Product Discontinuation 13/May/2009

  • 2,500

  • 集成电路 (IC)

  • 时钟/计时 - 时钟发生器，PLL，频率合成器

  • -

  • 锁相环路（PLL）

  • 是

  • 时钟

  • 时钟

  • 1

  • 1:2

  • 无/无

  • 120MHz

  • 是/无

  • 3.135 V ~ 5.5 V

  • 0°C ~ 70°C

  • 表面贴装

  • 16-SOIC（0.154"，3.90mm 宽）

  • 16-SOIC

  • 带卷 (TR)

  • 673M-01T

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