TECHNICAL DATA
KK4516B
Presettable Up/Down Counter
High-Voltage Silicon-Gate CMOS
The KK4516B Presettable Binary Up/Down Counter consists of four
synchronously clocked D-type flip-flops (with a gating structure to
provide T-type flip-flop capability) connected as counters. This counter
can be cleared by a high level on the RESET line, and can be preset to any
binary number present on the jam inputs by a high level on the PRESET
ENABLE line.
If the CARRY-IN input is held low, the counter advances up or down
on each positive-going clock transition. Synchronous cascading is
accomplished by connecting all clock inputs in parallel and connecting the
CARRY-OUT of a less significant stage to the CARRY-IN of a more
significant stage.
The KK4516B can be cascaded in the ripple mode by connecting the
CARRY-OUT to the clock of the next stage. If the UP/DOWN input
changes during a terminal count, the CARRY-OUT must be gated with
the clock, and the UP/DOWN input must change while the clock is high.
This method provides a clean clock signal to the subsequent
counting stage.
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Operating Voltage Range: 3.0 to 18 V
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Maximum input current of 1
碌A
at 18 V over full package-
temperature range; 100 nA at 18 V and 25掳C
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Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
KK4516BN Plastic KK
4516BD SOIC
T
A
= -55掳 to 125掳 C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
CL CI
X
H
L
L
X
X
PIN 16=V
CC
PIN 8= GND
X
X
U/D
X
H
L
X
X
PE R
L
L
L
H
X
L
L
L
L
H
Outputs
Mode
NO COUNT
COUNT UP
COUNT
DOWN
PRESET
RESET
X = don鈥檛 care
1
1
2
3
4
5
6
7
