鈻?/div>
sysIO鈩?Interfacing
鈥?LVCMOS 1.8, 2.5, 3.3 and LVTTL support for
standard board interfaces
鈥?SSTL 2/3 Class I and II support
鈥?HSTL Class I, III and IV support
鈥?GTL+, PCI-X for bus interfaces
鈥?LVPECL, LVDS and Bus LVDS differential support
鈥?Hot socketing
鈥?Programmable drive strength
Table 1. ispGDX2 Family Selection Guide
ispGDX2-64/E
I/Os
GDX Blocks
t
PD
t
S
t
CO
f
MAX
(Toggle)
Max Bandwidth
sysHSI Channels
2
LVDS/Bus LVDS (Pairs)
PLLs
Package
1. Max number of SERDES channels per device * 800Mbps
2. 鈥淓-Series鈥?does not support sysHSI.
3. f
MAX
(Toggle) * maximum I/Os divided by 2.
ispGDX2-128/E
128
8
3.2ns
2.0ns
3.1ns
330MHz
6.4Gbps
21Gbps
8
64
2
208-ball fpBGA
ispGDX2-256/E
256
16
3.5ns
2.0ns
3.2ns
300MHz
12.8Gbps
38Gbps
16
128
4
484-ball fpBGA
64
4
3.0ns
2.0ns
2.9ns
360MHz
SERDES
1, 2
3
3.2Gbps
11Gbps
4
32
2
100-ball fpBGA
Without SERDES
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