M24128-MN5T Datasheet

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M24256

M24128

256/128 Kbit Serial I虏C Bus EEPROM

Without Chip Enable Lines

s

s

Compatible with I

2

C Extended Addressing

Two Wire I

2

C Serial Interface

Supports 400 kHz Protocol

Single Supply Voltage:

鈥?4.5V to 5.5V for M24xxx

鈥?2.5V to 5.5V for M24xxx-W

s

8

1

PDIP8 (BN)

0.25 mm frame

s

s

s

s

s

s

s

s

Hardware Write Control

BYTE and PAGE WRITE (up to 64 Bytes)

RANDOM and SEQUENTIAL READ Modes

Self-Timed Programming Cycle

Automatic Address Incrementing

Enhanced ESD/Latch-Up Behavior

More than 100,000 Erase/Write Cycles

More than 40 Year Data Retention

8

1

SO8 (MN)

150 mil width

8

1

SO8 (MW)

200 mil width

DESCRIPTION

These I

2

C-compatible electrically erasable pro-

grammable memory (EEPROM) devices are orga-

nized as 32Kx8 bits (M24256) and 16Kx8 bits

(M24128), and operate down to 2.5 V (for the -W

version of each device).

The M24256B, M24128B and M24256A are also

available, and offer the extra functionality of the

chip enable inputs. Please see the separate data

sheets for details of these products.

The M24256 and M24128 are available in Plastic

Dual-in-Line and Plastic Small Outline packages.

These memory devices are compatible with the

I

2

C extended memory standard. This is a two wire

Figure 1. Logic Diagram

VCC

SCL

SDA

M24256

M24128

Table 1. Signal Names

SDA

Serial Data/Address Input/

Output

Serial Clock

Write Control

Supply Voltage

Ground

WC

SCL

WC

V

CC

V

SS

VSS

AI01882

June 2001

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