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MX23C8000QC-12 Datasheet

  • MX23C8000QC-12

  • 8M-BIT [1M x 8] CMOS MASK ROM

  • 908.56KB

  • 10页

  • MCNIX

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MX23C8000
8M-BIT [1M x 8] CMOS MASK ROM
FEATURES
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
1M x 8 organization
Single +5V power supply
Fast access time : 100/120/150/200ns
Totally static operation
Completely TTL compatible
鈥?Operating current : 40mA
鈥?Standby current : 100uA
鈥?Package
- 32 pin plastic DIP
- 32 pin plastic SOP
- 32 pin plastic PLCC
- 32 pin plastic TSOP
GENERAL DESCRIPTION
The MX23C8000 is a 5V only, 8M-bit, Read Only
Memory. It is organized as 1M words by 8 bits, oper-
ates from a single +5V supply, has a static standby mode,
and has an access time of 100/120/150/200ns. It is
designed to be compatible with all microprocessors and
similar applications in which high performance, large bit
storage and simple interfacing are important design con-
siderations.
MX23C8000 offers automatic power-down, with power-
down controlled by the chip enable (CE) input. When
CE goes high, the device automatically powers down
and remains in a low-power standby modes as long as
CE remains high.
MX23C8000 pin 24 may also be programmed either ac-
tive HIGH or LOW in order to eliminate bus contention
in multiple-bus microprocessor systems.
PIN CONFIGURATION
32 PDIP
A19
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A18
A17
A14
A13
A8
A9
A11
OE/OE
A10
CE/CE
Q7
Q6
Q5
Q4
Q3
32 SOP
A19
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
VSS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
10
19
18
17
VCC
A18
A17
A14
A13
A8
A9
A11
OE/OE
A10
CE/CE
Q7
Q6
Q5
Q4
Q3
VCC
A12
A15
A16
A19
A18
A17
32 PLCC
A7
A6
A5
A4
A3
A2
A1
A0
DQ
9
5
MX23C8000
32 TSOP
A14
A13
A8
A9
MX23C8000
4
1
32
30
29
MX23C8000
25
A11
OE/OE
A10
CE/CE
13
14
17
21
20
Q7
P/N:PM0137
VSS
A11
A9
A8
A13
A14
A17
A18
VCC
A19
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MX23C8000
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE/OE
A10
CE/CE
Q7
Q6
Q5
Q4
Q3
VSS
Q2
Q1
Q0
A0
A1
A2
A3
Q1
Q2
Q3
Q4
Q5
Q6
REV. 3.8, JUL. 16, 2001
1

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