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MX29F022NTQC-55 Datasheet

  • MX29F022NTQC-55

  • 2M-BIT[256K x 8]CMOS FLASH MEMORY

  • 890.81KB

  • 46页

  • MCNIX

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MX29F022/022N
2M-BIT[256K x 8]CMOS FLASH MEMORY
FEATURES
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262,144x 8 only
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Fast access time: 55/70/90/120ns
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Low power consumption
-30mA maximum active current
-1uA typical standby current@5MHz
Programming and erasing voltage 5V卤10%
Command register architecture
-Byte Programming (7us typical)
-Sector Erase (16K-Byte x1, 8K-Byte x 2, 32K-Byte
x1, and 64K-Byte x 3)
Auto Erase (chip & sector) and Auto Program
-Automatically erase any combination of sectors or
the whole chip with Erase Suspend capability.
-Automatically programs and verifies data atspecified
address
Erase Suspend/Erase Resume
-Suspends an erase operation to read data from,
or program data to, a sector that is not being erased,
then resumes the erase operation.
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Status Reply
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-Data polling & Toggle bit for detection of program and
erase cycle completion.
Chip protect/unprotect for 5V only system or 5V/12V
system
100,000 minimum erase/program cycles
Latch-up protected to 100mA from -1 to VCC+1V
Boot Code Sector Architecture
-T = Top Boot Sector
-B = Bottom Boot Sector
Hardware RESET pin
-Resets internal state machine to read mode
Low VCC write inhibit is equal to or less than 3.2V
Package type:
-32-pin PDIP
-32-pin PLCC
-32-pin TSOP (Type 1)
20 years data retention
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GENERAL DESCRIPTION
The MX29F022T/B is a 2-mega bit Flash memory
organized as 256K bytes of 8 bits only. MXIC's Flash
memories offer the most cost-effective and reliable read/
write non-volatile random access memory.The
MX29F022T/B is packaged in 32-pin PDIP, PLCC and
32-pin TSOP(I). It is designed to be reprogrammed and
erased in-system or in-standard EPROM programmers.
The standard MX29F022T/B offers access time as fast
as 55ns, allowing operation of high-speed microproc
essors without wait states. To eliminate bus contention,
the MX29F022T/B has separate chip enable (CE) and
output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F022T/B uses a command register to manage this
functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining
maximum EPROM compatibility.
MXIC's Flash technology reliably stores memory
contents even after 100,000 erase and program cycles.
The MXIC cell is designed to optimize the erase and
programming mechanisms. In addition, the combina-
tion of advanced tunnel oxide processing and low
internal electric fields for erase and programming
operations produces reliable cycling. The MX29F022T/
B uses a 5.0V
卤
10% VCC supply to perform the High
Reliability Erase and auto Program/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up
protection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
P/N:PM0556
REV. 1.1, JUN. 14, 2001
1

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