鈥?/div>
Maximum rated frequency: 133 MHz
Low cycle-to-cycle jitter
Input to output delay, less than 200ps
External feedback pin allows outputs to be synchronized
to the clock input
5V tolerant input*
Operates at 3.3V V
DD
Test mode allows bypass of the PLL for system testing
purposes (e.g., IBIS measurements)
Clock frequency multipliers 锟?frac12;x to 4x dependent on option
Space-saving Packages:
16-pin, 150-mil SOIC (W)
16-pin 173-mil TSSOP (L)
Functional Description
The PI6C2308 is a PLL-based, zero-delay buffer, with the ability
to distribute eight outputs of up to 133 MHz at 3.3 V. Two banks of
four outputs exist, and, depending on product option ordered, can
supply either reference frequency, prescaled half frequency, or
multiplied 2x or 4x input clock frequencies. The PI6C2308 family has
a power-sparing feature: when input SEL2 is 0, the component will
3-state one or both banks of outputs depending on the state of input
SEL1. A PLL bypass test mode also exists. This product line is
available in high-drive and industrial environment versions.
An external feedback pin is used to synchronize the outputs to the
input; the relationship between loading of this signal and the other
outputs determines the input-output delay.
The PI6C2308 is characterized for both commercial and industrial
operation.
* FB_IN and CLKIN must reference the same voltage thresh-
olds for the PLL to deliver zero delay skewing
Notice:
This device is subject to import restriction. Please refer
Block Diagram
FB_IN
CLKIN
梅2
PLL
OUTA1
OUTA2
OUTA3
OUTA4
梅2
OUTB1
Option (-2, -3)
PI6C2308 (-1, -1H, -2, -3, -4)
OUTB2
OUTB3
OUTB4
FB_IN
CLKIN
PLL
to the Import Restriction Notice under the Ordering Information
section.
Pin Configuration PI6C2308
MUX
Option (-3, -4)
SEL1
SEL2
Decode
Logic
CLKIN
OUTA1
OUTA2
VDD
GND
OUTB1
OUTB2
SEL2
16
1
15
2
3
16-Pin
14
4
W, L
13
12
5
11
6
10
7
9
8
FB_IN
OUTA4
OUTA3
VDD
GND
OUTB4
OUTB3
SEL1
MUX
OUTA1
OUTA2
OUTA3
SEL2
SEL1
Decode
Logic
梅2
MUX
OUTA4
PI6C2308-6
OUTB1
OUTB2
OUTB3
OUTB4
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PS8384D
12/07/01
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