P4C150
P4C150
ULTRA HIGH SPEED 1K X 4
RESETTABLE STATIC CMOS RAM
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
鈥?10/12/15/20/25 ns (Commercial)
鈥?15/20/25/35 ns (Military)
Chip Clear Function
Low Power Operation
鈥?713 mW Active
鈥?0 ns (Commercial)
鈥?550 mW Active
鈥?5 ns (Commercial)
Standard Pinout (JEDEC Approved)
鈥?24-Pin 300 mil DIP
鈥?24-Pin 300 mil SOIC
鈥?28-Pin LCC (350 x 550 mils)
鈥?24-Pin CERPACK
Single 5V
卤
10% Power Supply
Separate Input and Output Ports
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
DESCRIPTION
The P4C150 is a 4,096-bit ultra high-speed static RAM
organized as 1K x 4 for high speed cache applications.
The RAM features a reset control to enable clearing all
words to zero within two cycle times. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs and outputs are fully TTL-compat-
ible. The RAM operates from a single 5V
卤
10% tolerance
power supply.
Access times as fast as 10 nanoseconds are available
permitting greatly enhanced system operating speeds.
Time required to reset is only 20 ns for the 10 ns SRAM.
CMOS is used to reduce power consumption to a low
level.
The P4C150 is available in 24-pin 300 mil DIP and SOIC
packages providing excellent board level densities. The
device is also available in a 28-pin LCC package as well
as a 24-pin FLATPACK for military applications.
FUNCTIONAL BLOCK DIAGRAM
A
A
A
A
A
A
I
1
I
2
I
3
I
4
PIN CONFIGURATIONS
ROW
SELECT
4,096-BIT
MEMORY
ARRAY
A
1
A
2
A
3
A
4
A
5
A
6
I
1
I
2
O
1
O
2
GND
2
3
4
5
6
7
8
9
10
11
12
23
22
21
20
19
18
17
16
15
14
13
A
9
A
8
A
7
RS
CS
WE
OE
I
4
I
3
O
4
O
3
A2
A3
A4
A5
NC
A6
I1
I2
O1
3
4
5
6
7
8
9
10
11
12
13
O2
14 15 16
O3
GND
NC
2
1
28
A1
A0
1
24
A9
27
26
25
24
23
22
21
20
19
18
17
O4
A
0
V
CC
NC
V CC
A8
A7
RS
CS
NC
WE
OE
I4
I3
INPUT
DATA
CONTROL
O
1
O
2
COLUMN I/O
O
3
O
4
CS
WE
RS
OE
A
COLUMN
SELECT
A
A
A
DIP (P4, D4), SOIC (S4)
CERPACK (F4) SIMILAR
TOP VIEW
LCC (L5)
TOP VIEW
Means Quality, Service and Speed
1Q97
25
1
2
3
4
5
6
7
8
