LOW-POWER 9-BIT
INVERTER
SY100S321
FEATURES
s
Max. propagation delay of 700ps
s
I
EE
min. of 鈥?5mA
s
Extended supply voltage option:
V
EE
= 鈥?.2V to 鈥?.5V
s
Voltage and temperature compensation for
improved noise immunity
s
70% faster than Fairchild 300K at lower power
s
Internal 75K
鈩?/div>
input pull-down resistors
s
Function and pinout compatible with Fairchild F100K
s
Available in 24-pin CERPACK and 28-pin PLCC
packages
DESCRIPTION
The SY100S321 is a monolithic 9-bit inverter. The device
contains nine inverting buffer gates with single input and
output.
PIN CONFIGURATIONS
D
4
V
CCA
V
EES
O
4
O
5
O
6
4
3
Top View
PLCC
J28-1
2
1
28
27
26
19 20 21 22 23 24 25
V
EES
D
5
D
6
D
7
V
EE
V
EES
V
CCA
12
13
14
15
16
17
18
11 10 9 8 7 6 5
O
7
O
8
V
CCA
V
CC
V
CC
O
9
O
1
BLOCK DIAGRAM
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
O
1
O
2
D
8
D
9
V
CCA
O
3
O
2
D
1
D
2
D
3
D
8
V
CCA
V
EE
D
9
D
7
D
1
O
3
O
4
O
5
O
6
O
7
O
8
O
9
1
2
3
4
5
6
24 23 22 21 20 19
18
Top View
Flatpack
F24-1
17
16
15
14
D
6
D
5
D
4
V
CCA
Q
4
Q
5
Q
6
D
2
D
3
V
CCA
O
3
O
2
13
7 8 9 10 11 12
O
9
V
CC
O
1
PIN NAMES
Pin
D
1
鈥?D
9
Q
1
鈥?Q
9
V
EES
V
CCA
Function
Data Inputs
Data Outputs
V
EE
Substrate
V
CCO
for ECL Outputs
V
CCA
Rev.: G
O
8
O
7
Amendment: /0
Issue Date: July, 1999
1
1
2
3
4
5
