Max. shift frequency of 600MHz
Max. Clock to Q delay of 1200ps
min. of 鈥?50mA
鈩?/div>
input pull-down resistors
s
70% faster than Fairchild 300K at lower power
s
Function and pinout compatible with Fairchild F100K
s
Available in 24-pin CERPACK and 28-pin PLCC
packages
SY100S341
DESCRIPTION
The SY100S341 offer eight D-type, edge-triggered flip-
flops with both individual inputs for parallel operation as
well as serial inputs for bidirectional shifting, and are
designed for use in high-performance ECL systems. Data
is clocked into the flip-flops on the rising edge of the clock.
The mode of operation is selected by two Select inputs
(S
0
, S
1
) which determine if the device performs a shift, hold
or parallel entry function, as described in the Truth Table.
The inputs on these devices have 75K鈩?pull-down resistors.
PIN CONFIGURATIONS
P
6
P
7
V
EES
Q
7
Q
6
4
3
2
1
28
27
26
11 10 9 8 7 6 5
P
4
CP
V
EE
V
EES
S
0
12
13
14
15
16
17
18
19 20 21 22 23 24 25
Top View
PLCC
J28-1
Q
5
Q
4
V
CCA
V
CC
V
CC
Q
3
Q
2
PIN NAMES
Label
CP
S
0
鈥?S
1
D
0
鈥?D
7
P
0
鈥?P
7
Q
0
鈥?Q
7
V
EES
V
CCA
Function
Clock Pulse Input
Select Inputs
Serial Inputs
Parallel Inputs
Data Outputs
V
EE
Substrate
V
CCO
for ECL Outputs
S
1
P
3
D
7
P
5
S
1
S
0
V
EE
V
EES
D
0
Q
0
Q
1
P
2
P
1
P
0
D
0
Q
0
Q
1
24 23 22 21 20 19
1
18
2
3
4
5
6
Top View
Flatpack
F24-1
17
16
15
14
CP
P
4
P
2
P
1
P
0
P
3
P
5
P
6
P
7
D
7
Q
7
Q
8
13
7 8 9 10 11 12
Q
3
V
CC
V
CCA
Q
2
Q
4
Q
5
Rev.: G
Amendment: /0
1
Issue Date: July, 1999
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