U6264A
Features
F
8192 x 8 bit static CMOS RAM
F
70 and 100 ns Access Times
F
Common data inputs and
outputs
F
Three-state outputs
F
Typ. operating supply current
F
F
F
F
F
F
F
F
F
F
F
ESD protection > 2000 V
(MIL STD 883C M3015.7)
F
Latch-up immunity > 100 mA
F
Packages: PDIP28 (600 mil)
Description
Standard 8K x 8 SRAM
DQ0 - DQ7. After the address
change, the data outputs go High-Z
until the new read information is
available. The data outputs have no
preferred state. If the memory is
driven by CMOS levels in the active
state, and if there is no change of
the address, data input and control
signals W or G, the operating cur-
rent (at I
O
= 0 mA) drops to the
value of the operating current in the
Standby mode. The Read cycle is
finished by the falling edge of E2 or
W, or by the rising edge of E1,
respectively.
Data retention is guaranteed down
to 2 V. With the exception of E2, all
inputs consist of NOR gates, so that
no pull-up/pull-down resistors are
required. This gate circuit allows to
achieve low power standby require-
ments by activation with TTL-levels
too.
If the circuit is inactivated by
E2 = L, the standby current (TTL)
drops to 150
碌A
typ.
SOP28 (300 mil)
SOP28 (330 mil)
70 ns: 45 mA
100 ns: 37 mA
Data retention current
at 3 V: < 10
碌A
(standard)
Standby current standard < 30
碌A
Standby current low power
(L) < 10
碌A
Standby current very low power
(LL) < 1
碌A
Standby current for LL-version
at 25
掳C
and 5 V: typ. 50 nA
TTL/CMOS-compatible
Automatic reduction of power
dissipation in long Read or Write
cycles
Power supply voltage 5 V
Operating temperature ranges:
0 to 70
掳C
-25 to 85
掳C
-40 to 85
掳C
Quality assessment according to
CECC 90000, CECC 90100 and
CECC 90111
The U6264A is a static RAM manu-
factured using a CMOS process
technology with the following ope-
rating modes:
- Read
- Standby
- Write
- Data Retention
The memory array is based on a
6-transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously. According to the
information of W and G, the data
inputs, or outputs, are active.
During the active state (E1 = L and
E2 = H), each address change
leads to a new Read or Write cycle.
In a Read cycle, the data outputs
are activated by the falling edge of
G, afterwards the data word read
will be available at the outputs
Pin Configuration
n.c.
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
VCC
W (WE)
E2 (CE2)
A8
A9
A11
G (OE)
A10
E1 (CE1)
DQ7
DQ6
DQ5
DQ4
DQ3
Pin Description
Signal Name
A0 - A12
DQ0 - DQ7
E1
E2
G
W
VCC
VSS
n.c.
Signal Description
Address Inputs
Data In/Out
Chip Enable 1
Chip Enable 2
Output Enable
Write Enable
Power Supply Voltage
Ground
not connected
PDIP
22
SOP
21
20
19
18
17
16
15
Top View
December 12, 1997
1
1
2
3
4
5
6
7
8
9
