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JEDEC Standard Pin Configuration
GENERAL DESCRIPTION
The WS27C256L is a performance oriented 256K UV Erasable Electrically Programmable Read Only Memory
organized as 32K words x 8 bits/word. It is manufactured using an advanced CMOS technology which enables it to
operate at speeds up to 120 nsecs. The memory was designed utilizing WSI's patented self-aligned split gate
EPROM cell, resulting in a low power device with a very cost effective die size.
The WS27C256L 256K EPROM provides 32K of 8 bit wide code store capacity for DSP, microprocessor, and
microcontroller-based systems. Its 120 nsec access time over the full Military temperature range provides the
potential of no-wait state operation. And where this parameter is important, the WS27C256L provides the user with
a very fast 35 nsec T
OE
output enable time.
The WS27C256L is offered in a 28 pin 300 mil skinny CERDIP or the standard 600 mil CERDIP, and also in a
32 pad Ceramic Leadless Chip Carrier (CLLCC) for surface mount applications. All packages incorporate the
standard JEDEC EPROM pinout.
PIN CONFIGURATION
TOP VIEW
Chip Carrier
A
7
A
12
V
PP
NC
V
CC
A
14
A
13
CERDIP
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
O
0
32 31 30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
1
O
1
O
2
GND
4 3 2
A
8
A
9
A
11
NC
OE
A
10
CE/PGM
O
7
O
6
NC O
3
O
4
O
5
V
PP
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
A14
A13
A8
A9
A11
OE
A10
CE/PGM
O
7
O
6
O
5
O
4
O
3
PRODUCT SELECTION GUIDE
PARAMETER
Address Access Time (Max)
Chip Select Time (Max)
Output Enable Time (Max)
WS27C256L-12
120 ns
120 ns
35 ns
WS27C256L-15
150 ns
150 ns
40 ns
WS27C256L-20
200 ns
200 ns
40 ns
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