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WSF128K16-37H1C Datasheet

  • WSF128K16-37H1C

  • 128K X 16 SRAM /FLASH MODULE SMD 5962-96900

  • 539.34KB

  • 15页

  • ETC

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WSF128K16-XXX
128Kx16 SRAM/FLASH MODULE, SMD 5962-96900
FEATURES
n
n
n
Access Times of 35ns (SRAM) and 70ns (FLASH)
n
Access Times of 70ns (SRAM) and 120ns (FLASH)
n
Packaging
鈥?66-pin, PGA Type, 1.075 inch square HIP, Hermetic
Ceramic HIP (Package 400)
鈥?66-pin, PGA Type, 1.185 inch square HIP, Hermetic
Ceramic HIP (Package 401)
鈥?68 lead, Hermetic CQFP (G1U), 22.4mm (0.880
inch) square (Package 519). Designed to fit JEDEC
68 lead 0.990鈥?CQFJ footprint (Fig. 2)
n
128Kx16 SRAM
n
128Kx16 5V FLASH
n
Organized as 128Kx16 of SRAM and 128Kx16 of Flash
Memory with separate Data Buses
n
Both blocks of memory are User Configurable as
256Kx8
n
Low Power CMOS
n
Commercial, Industrial and Military Temperature Ranges
n
TTL Compatible Inputs and Outputs
n
n
n
n
Built-in Decoupling Caps and Multiple Ground Pins for
Low Noise Operation
Weight
鈥?WSF128K16-XHX - 13 grams typical
鈥?WSF128K16-H1X - 13 grams typical
鈥?WSF128K16-XG1UX - 5 grams typical
FLASH MEMORY FEATURES
n
n
10,000 Erase/Program Cycles
Sector Architecture
鈥?8 equal size sectors of 16K bytes each
鈥?Any combination of sectors can be concurrently
erased.
Also supports full chip erase
5 Volt Programming; 5V 卤 10% Supply
Embedded Erase and Program Algorithms
Hardware Write Protection
Page Program Operation and Internal Program Control
Time.
Note: For programming information refer to Flash Programming 1M5
Application Note.
F
IG
.1
P
IN
C
ONFIGURATION
F
OR
WSF128K16-XHX A
ND
WSF128K16-XH1X
T
OP
V
IEW
FD
0-15
SD
0-15
A
0-16
SWE
1-2
SCS
1-2
OE
V
CC
GND
NC
FWE
1-2
FCS
1-2
P
IN
D
ESCRIPTION
Flash Data Inputs/Outputs
SRAM Data Inputs/Outputs
Address Inputs
SRAM Write Enable
SRAM Chip Selects
Output Enable
Power Supply
Ground
Not Connected
Flash Write Enable
Flash Chip Select
B
LOCK
D
IAGRAM
May 2001 Rev. 5
1
White Electronic Designs Corporation 鈥?(602) 437-1520 鈥?www.whiteedc.com

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