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XR-2207ID Datasheet

  • XR-2207ID

  • Voltage-Controlled Oscillator

  • 249.92KB

  • 24页

  • EXAR   EXAR

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XR-2207
...the analog plus company
TM
Voltage-Controlled
Oscillator
June 1997鈥?
FEATURES
D
Excellent Temperature Stability (20ppm/掳C)
D
Linear Frequency Sweep
D
Adjustable Duty Cycle (0.1% to 99.9%)
D
Two or Four Level FSK Capability
D
Wide Sweep Range (1000:1 Minimum)
D
Logic Compatible Input and Output Levels
D
Wide Supply Voltage Range ($4V to
$13V)
D
Low Supply Sensitivity (0.1% /V)
D
Wide Frequency Range (0.01Hz to 1MHz)
D
Simultaneous Triangle and Squarewave Outputs
GENERAL DESCRIPTION
The XR-2207 is a monolithic voltage-controlled oscillator
(VCO) integrated circuit featuring excellent frequency
stability and a wide tuning range. The circuit provides
simultaneous triangle and squarewave outputs over a
frequency range of 0.01Hz to 1MHz. It is ideally suited for
FM, FSK, and sweep or tone generation, as well as for
phase-locked loop applications.
ORDERING INFORMATION
Part No.
XR-2207M
XR-2207CP
XR-2207D
XR-2207ID
APPLICATIONS
D
FSK Generation
D
Voltage and Current-to-Frequency Conversion
D
Stable Phase-Locked Loop
D
Waveform Generation
鈥?Triangle, Sawtooth, Pulse, Squarewave
D
FM and Sweep Generation
The XR-2207 has a typical drift specification of 20ppm/掳C.
The oscillator frequency can be linearly swept over a
1000:1 range with an external control voltage; and the
duty cycle of both the triangle and the squarewave
outputs can be varied from 0.1% to 99.9% to generate
stable pulse and sawtooth waveforms.
Package
14 Lead 300 Mil CDIP
14 Lead 300 Mil PDIP
16 Lead 300 Mil JEDEC SOIC
16 Lead 300 Mil JEDEC SOIC
Operating
Temperature Range
-55掳C to +125掳C
0掳C to +70掳C
0掳C to +70掳C
-40掳C to +85掳C
BLOCK DIAGRAM
C1
C1
R1
R2
R3
R4
2
3
V
CC
GND
1
10
BIAS
11
A1
14
13
A2
12
Timing
Capacitor
4
5
6
7
Timing
Resistors
Rev. 2.02
E1975
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538
z
(510) 668-7000
z
FAX (510) 668-7017
1
脦
脦
脦
TWO
SWO
V
EE
BKI2
BKI1
Triangle Wave Out
Square Wave Out
VCO
Current
Switches
9
8
Binary
Keying
Inputs
Figure 1. Block Diagram

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